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A Hardware Accelerator for Quantile Estimation of Network Packet Attributes

A Hardware Accelerator for Quantile Estimation of Network Pa...

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Euromicro symposium on Digital System Design

作者： Carolina Gallardo-Pavesi Yaime Fernandez Javier E. Soto Cecilia Hernández Miguel Figueroa Department of Electrical Engineering Department of Computer Science Universidad de Concepcion Concepción Chile Center of Biotechnology and Bioengineering (CeBiB) Advanced Center for Electrical and Electronics Engineering (AC3E)

ISBN: (数字)9798350380385

ISBN: (纸本)9798350380392

Measuring statistical properties of network traffic can improve our understanding of traffic distribution and help us detect short and long-term anomalies. However, computing the exact value of these properties requires significant storage and computation, which limits their application in high-speed networks. Hardware accelerators provide the computational power to process a large sequence of network packets with high throughput and low latency, but their performance is ultimately limited by the amount of on-chip memory available on the device. Consequently, researchers have proposed sketch-based algorithms to estimate properties of a data stream with sub linear memory and theoretical estimation error bounds. In this paper, we present a streaming algorithm and hardware accelerator for quantile estimation, which is based on the architecture of the KLL sketch. Implemented on an AMD Virtex XCU55 UltraScale+ FPGA, the accelerator operates at a clock frequency of 356 MHz, thereby achieving a minimum line rate of 182 Gbps and a maximum estimation latency of 4.33 µs. When processing a set of 10 real traffic traces of up to 123 million packets, the accelerator estimates 1000 packet-size quantiles per trace with a median error of 0.39% or less, and a maximum error of 1.3% or less across all traces.

关键词： performance evaluation Estimation error Memory management Telecommunication traffic Logic gates throughput System-on-chip Low latency communication Hardware acceleration Field programmable gate arrays

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MANET Routing Protocol performance Comparison: DSDV, AODV, and DSR

MANET Routing Protocol Performance Comparison: DSDV, AODV, a...

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Innovative Approaches in Smart Technologies (ISAS), International symposium on

作者： Kamred Udham Singh Ankit Kumar Gaurav Kumar Tanupriya Choudhury Ketan Kotecha School of Computing Graphic Era Hill University Dehradun India Department of Computer Engineering & Applications GLA University Mathura UP India CSE Dept. Symbiosis Institute of Technology Symbiosis International (Deemed University) Pune Maharashtra India Symbiosis Centre for Applied Artificial Intelligence Symbiosis Institute of Technology Symbiosis International (Deemed University) Pune Maharashtra India

Mobile Ad hoc Networks (MANETs) may self-configure and rely on wireless connections rather than a permanent infrastructure; hence this research delves into their intricacies. this research aims to better understand how MANETs function. MANETs are characterized by their high degree of dynamism and adaptability to changes in network architecture. these networks are made up of mobile nodes that are independent and can perform the functions of both a host and a router. Having said that, this flexibility does provide a number of substantial issues, notably in the area of routing. the unexpected and fluid nature of MANET topology, which is related to the mobility of the nodes, makes routing a hard process. the effectiveness of the network is strongly reliant on the efficacy of the routing protocols that are implemented; therefore this is an important consideration. Our study analyses the capabilities of three popular MANET routing protocols: DSDV, AODV, and DSR. these protocols must be compared using end-to-end latency, packet delivery percentage, and lost packet ratio across different network densities and mobility patterns. In our simulations, we seek to replicate a wide variety of situations that can occur in the real world by altering the number of nodes, the connection counts, and the pause periods. these simulations are carried out with the help of the Network Simulator 2 (version 2.35), a programme that is well-known for its use in network research. Additionally, the graphical representation of the data is carried out with the assistance of gnuplot. Our first findings suggest that AODV has a significant advantage over DSDV and DSR when it comes to handling the dynamic networking environment of MANETs more effectively. this is especially true in situations characterised by high node mobility and variable network density. this research not only highlights the necessity of selecting the appropriate routing protocol in MANETs, but it also offers a thorough framework fo

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Automatic Detection of Peripheral Facial Landmarks Using 3D Facial Data

Automatic Detection of Peripheral Facial Landmarks Using 3D ...

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International Conference on Image and Vision computing New Zealand, IVCNZ

作者： Mehraan Chowdhury Mohammed Bennamoun Farid Boussaid Syed Mohammed Shamsul Islam Department of Computer Science and Software Engineering University of Western Australia Perth Australia Department of Electrical Electronic and Computer Engineering University of Western Australia Perth Australia Discipline of Computing and Security Edith Cowan University Perth Australia

ISBN: (数字)9798331518776

ISBN: (纸本)9798331518783

Facial landmarking research has traditionally fo-cused on midface landmarks, largely overlooking peripheral facial features that are crucial in specialized medical applications. this study addresses this gap by developing a novel model to detect 12 peripheral landmarks, which are valuable in clinical scenarios such as obstructive sleep apnea detection and facial palsy assessment. Using the FRGC v2 dataset of 3D facial scans, we manually annotated a subset of 900 scans with peripheral landmarks following a rigorous pre-processing protocol. Building upon a high-performance deep learning model initially designed for midface landmark detection, we restructured its architecture to predict peripheral landmarks by modifying its output layers and training it from scratch using 2D projections of 3D scans. We conducted a comprehensive set of experiments, systematically testing different input configurations by varying both the number of images per scan (16, 32, and 64) and the image types (mesh-only, RGB, and depth maps). the model demonstrated its potential by achieving a mean error of 10.72 mm, highlighting the promise of deep learning techniques in addressing the complex challenge of peripheral landmark detection. these findings underscore the model's capability to support niche medical applications and open pathways for future advancements that could refine its accuracy, ultimately contributing to improved diagnostic tools in healthcare.

关键词： Training Deep learning Solid modeling Biomedical equipment three-dimensional displays Protocols Medical services Transforms Sleep apnea Testing

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A 17 dB high Gain 65% PAE Wideband CMOS Integrated Power Amplifier Design in 180 nm Process for Wireless Power Transfer Applications

A 17 dB High Gain 65% PAE Wideband CMOS Integrated Power Amp...

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Midwest symposium on Circuits and Systems (MWSCAS)

作者： Rafsan Mahin Ifana Mahbub Department of Electrical and Computer Engineering The University of Texas at Dallas Richardson TX

ISBN: (数字)9798350387179

ISBN: (纸本)9798350387186

this paper presents the design of a high gain, high power added efficiency (PAE) wideband power amplifier (PA) in the standard 180nm CMOS process for wireless power transfer (WPT) applications. the proposed PA design utilizes a single stage common-source architecture, working in the ultra-wideband (UWB) frequency range (3.1 - 10.6 GHz). the amplifying stage utilizes a single NMOS transistor where the scaling factor of the transistor is optimized to generate the highest transconductance, $g_{m}$ value, and thus maximize the available power gain from the transistor. An analysis and optimization of the scaling factor is also performed to generate the optimal balance between achieving a $\text{high} \ g_{m}$ while also minimizing the insertion loss from the quality factor of the integrated on-chip inductor so that a higher overall gain can be achieved. the designed PA achieves a maximum gain of 17.4 dB at 6.5 GHz frequency and the $P_{1dB}$ compression point occurs at an input power of 7 dBm. In addition, a $-3\mathbf{dB}S_{21}$ gain bandwidth of 2.19 GHz (5.29 - 7.48 GHz) can be obtained from the proposed PA design. At the $P_{1dB}$ compression point, the PA is able to generate an output power of 24.4 dBm at 6.5 GHz frequency for 3.3 V drain supply voltage. the proposed PA is able to achieve a peak PAE performance of 65.6% at the 16 dBm input power. By employing a single stage L-shaped shunt inductor and series capacitor as part of the input and output matching network, $> 60\%$ PAE performance is achieved over a wide bandwidth of 2 GHz from 5.5 - 6.5 GHz.

关键词： Q-factor Power amplifiers Insertion loss Wireless power transfer System-on-chip Transistors Inductors

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Super-Resolution MRH Reconstruction for Mouse Models 16th

Super-Resolution MRH Reconstruction for Mouse Models

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16th International Conference on Brain Informatics, BI 2023

作者： Ha, Juhyung Wang, Nian Maharjan, Surendra Zhang, Xuhong Computer Science Department Luddy School of Informatics University of Indiana Bloomington47408 United States Department of Radiology and Imaging Sciences Indiana University Indianapolis46202 United States Stark Neurosciences Research Institute Indiana University Indianapolis46202 United States

ISBN: (纸本)9783031430749

Magnetic Resonance Imaging (MRI) has been widely used in pathology research and plays a vital role in clinical diagnoses. However, obtaining high-resolution MRI stays a significant challenge as the process is restrained by the hardware capacity, sampling time, signal-to-noise ratio (SNR), and subject comfort. Compared to MRI, Magnetic Resonance Histology (MRH) is more costly as it has a higher spatial resolution. Deep learning models have recently succeeded in MRI Super-Resolution (SR) reconstruction from Low-Resolution (LR) images. However, it is still hard to overcome artifacts during the restoration process. the models usually have limitations in the high-frequency component representations, which can reflect finer details as in MRH images. In this work, we propose an imaging restoration framework that can conduct SR reconstruction for the whole mouse brain MRH images, and the model is based on a deep dense network. We first synthesized LR images from HR ones to train the proposed model, and then we quantitatively compared the model performance with existing methods proposed for the human brain and natural images. Finally, we demonstrated the superior visual reconstruction and interpretation of the proposed model compared to prior works. © 2023, the Author(s), under exclusive license to Springer Nature Switzerland AG.

关键词： Image reconstruction

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Large Scale Cryogenic Integration Approach for Superconducting high-performance computing

Large Scale Cryogenic Integration Approach for Superconducti...

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Electronic Components and Technology Conference (ECTC)

作者： Rabindra N. Das Vladimir Bolkhovsky Sergey K Tolpygo Pascale Gouker Leonard M. Johnson Eric A. Dauler Mark A. Gouker Quantum Information and Integrated Nanosystems Group MIT Lincoln Laboratory Lexington MA

Superconducting single-flux-quantum-based (SFQ) digital integrated circuits (ICs) are a promising candidate for high-speed and ultralow energy dissipation computing systems. Circuits based on several versions of SFQ-type logic, RQL, and AQFP logic have been demonstrated with complexities reaching up to a few tens of thousands of gates. Packaging many superconducting ICs using microbump (15μm or less) technology and performing high throughput, nearly lossless data transfer between various superconducting and/or CMOS chips are highly desirable for a hybrid superconducting computer architecture, but this density has not yet been demonstrated. An efficient way to achieve this goal is to couple the chips through a passive superconductive multichip module (S-MCM) that distributes information between integrated circuits utilizing lossless superconducting transmission lines. Here we show implementation of such a superconducting base using well-defined impedance lines to couple multiple ICs to enable a cryogenic integration approach for possible future hybrid superconducting computing systems. the use of indium-based microbumps to form interconnects between an S-MCM and superconducting ICs, and its electrical performance, are discussed. Optimized microbumps were used to fabricate interconnections on a large S-MCM by using thermocompression(TC) bonding. From 17200 to 68800 microbumps fabricated in a 5 mm × 5 mm active area of an S-MCM, having pitches ranging from 35 μm to 15 μm, were bonded with a superconducting IC to create a daisy chain structure. In addition, a large active area (10 mm × 10 mm) flip-chip having continuous niobium daisy chains with up to 77,500 bumps with 15 μm bump diameter and 35 μm pitch was also demonstrated. As a case study, an optimized microbump interconnect construction for attaching 16 superconducting chips with a large 32 mm × 32 mm superconducting base was fabricated and tested at room temperature and 4.2 K to study the structural and electrical

关键词： Superconducting integrated circuits Josephson junctions Superconducting epitaxial layers Superconducting transmission lines Integrated circuit interconnections Indium Bonding

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A Lightweight Folded Keccak-Based SHA-3 for Resource-Constrained Embedded Security

A Lightweight Folded Keccak-Based SHA-3 for Resource-Constra...

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IEEE International symposium on Embedded Multicore Socs (MCSoC)

作者： Siqi Xiong Dongsheng Liu Jiahao Lu Aobo Li Tianze Huang Chenjun Yang Ang Hu Yuejun Zhang School of Integrated Circuits Huazhong University of Science and Technology Wuhan China Faculty of Electrical Engineering and Computer Science Ningbo University Ningbo China

ISBN: (数字)9798331530471

ISBN: (纸本)9798331530488

Secure Hash Algorithm 3 (SHA-3) is a crucial component in modern cryptographic systems, particularly in applications demanding high security and efficiency. For example, it is vital in System-on-Chip (SoC) applications and resource-constrained environments like IoT devices and embedded systems. However, existing SHA-3 designs face challenges regarding resource limitations and computational efficiency. this paper presents a slice-oriented folded SHA-3 architecture supporting multiple folding parameters for embedded SoC in FPGA implementations. It targeted crypto engines and other resource-limited cryptographic applications. We identified the optimal folding direction and introduced a round function rescheduling method. We proposed a novel interleaving storage strategy to resolve clock cycle delays caused by data dependencies. Additionally, we proposed a simplified round constant mechanism to minimize area consumption. the slice-based folded architecture across all parameter sets are implemented on Xilinx Virtex-7, controlled by an ARM Cortex-M4 processor. Our design achieved a maximum frequency of 324 MHz and the compact implementation, resulting in the 92% reduction in slices compared to basic design. Furthermore, it offered 70% area reduction, 1.44× throughput improvement, and 1.91× gain in efficiency over the previous state of the art. these results show the potential of our design for resource-limited security applications, providing both hardware resource savings and enhanced performance.

关键词： Trusted computing Program processors Random access memory Process control throughput Computational efficiency System-on-chip Cryptography Field programmable gate arrays Clocks

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Early-Stage Cholangiocarcinoma Detection Using Surface-Enhanced Raman Spectroscopy and 1D CNN with Discrete Wavelet Transform

Early-Stage Cholangiocarcinoma Detection Using Surface-Enhan...

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Biomedical Engineering International Conference (BMEiCON)

作者： Pobporn Danvirutai Chawalit Pairojkul Sartra Wongthanavasu Chavis Srichan Somchai Pinlaor College of Computing Khon Kaen University Khon Kaen Thailand Department of Parasitology Faculty of Medicine Khon Kaen University Khon Kaen Thailand Computer Engineering department and Biomedical Engineering department Faculty of Engineering Khon Kaen University Thailand

ISBN: (数字)9798331505431

ISBN: (纸本)9798331505448

this Early detection of cholangiocarcinoma (CCA) is critical for improving patient prognosis and survival rates. Surface-Enhanced Raman Spectroscopy (SERS) offers a promising non-invasive diagnostic tool due to its high sensitivity and specificity. In this study, we propose a novel approach combining Discrete Wavelet Transform (DWT) and a one-dimensional Convolutional Neural Network (lD CNN) for the detection and differentiation of first stage CCA from precancerous, inflammation, and healthy states using SERS data. Our method is compared with a traditional Principal Component Analysis (PCA) followed by Support Vector Machine (SVM) classification. In contrast, the PCA + SVM method could only differentiate late-stage CCA and healthy states due to the nonlinearity of the SERS dataset. Receiver Operating Characteristic (ROC) curve analysis further validates the superior performance of our proposed method. We studied on hamster serum and the concept can be extended to human serum in the near future work.

关键词： Support vector machines Accuracy Surface waves Raman scattering Transforms Receivers Sensitivity and specificity Discrete wavelet transforms Convolutional neural networks Principal component analysis

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Synergistic Q-Functions and Risk Weighted Actor-Critic for Offline Reinforcement Learning

Synergistic Q-Functions and Risk Weighted Actor-Critic for O...

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International Conference on Communication Software and Networks, ICCSN

作者： Binyi Bai Yaxin Yu Zhaopeng Fan Tian Yang Jiacheng Wang Jiashuo Yao School of Computer Science and Engineering Northeastern University Shenyang China

ISBN: (数字)9798331506322

ISBN: (纸本)9798331506339

Offline reinforcement learning (RL) algorithms, which rely solely on static datasets, face significant challenges: (1) Insufficient coverage of the offline dataset can lead to substantial errors when the agent selects actions outside the dataset for policy learning, causing a severe deviation between the training policy and the behavior policy. (2) the quality of offline data entirely dictates the training of offline RL policies, resulting in poor generalization ability in new environments. To address these issues, we propose a novel Synergistic Q-functions and Risk Weighted Algorithm (SQRWAC). this algorithm innovatively integrates strategies in both the critic and actor designs to tackle environmental incompleteness and data sparsity. the critic incorporates a risk factor in policy evaluation to prioritize actions with high impact on rewards, optimizing long-term returns. Simultaneously, by synergistically computing the target value function using the Q-function, the algorithm alleviates over-fitting and enhances decision-making robustness. Comparative experiments in the MuJoCo simulation environment demonstrate that SQRWAC outperforms existing baseline algorithms, showing superior performance and higher data utilization efficiency across various standard RL tasks.

关键词： Training Software algorithms Decision making Reinforcement learning Stability analysis Software Robustness Standards Faces Engines

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FASTER: Facilitating Analysis and Synthesis Technologies for Effective Reconfiguration

FASTER: Facilitating Analysis and Synthesis Technologies for...

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Euromicro symposium on Digital System Design

作者： D. Pnevmatikatos T. Becker A. Brokalakis K. Bruneel G. Gaydadjiev W. Luk K. Papadimitriou I. Papaefstathiou O. Pell C. Pilato M. Robart M.D. Santambrogio D. Sciuto D. Stroobandt T. Todman Foundation for Research and Technology Hellas FORTH Greece Imperial College London UK Synelixis Greece Ghent University-IBBT Belgium Chalmers University of Technology Sweden Maxeler Technologies UK Politecnico di Milano Italy ST-Microelectronics Italy

the FASTER project aims to ease the definition, implementation and use of dynamically changing hardware systems. Our motivation stems from the promise reconfigurable systems hold for achieving better performance and extending product functionality and lifetime via the addition of new features that work at hardware speed. this is a clear advantage over the more straightforward software component adaptivity. However, designing a changing hardware system is both challenging and time consuming. the FASTER project will facilitate the use of reconfigurable technology by providing a complete methodology that enables designers to easily specify, analyse, implement and verify applications on platforms with general-purpose processors and acceleration modules implemented in the latest reconfigurable technology. To better adapt to different application requirements, the tool-chain will support both region-based and micro-reconfiguration and provide a flexible run-time system that will efficiently manage the reconfigurable resources. We will use applications from the embedded, high performance computing, and desktop domains to demonstrate the potential benefits of the FASTER tools on metrics such as performance, power consumption and total ownership cost.

关键词： Hardware Field programmable gate arrays computer architecture XML Schedules Software Power demand

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