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检索条件"任意字段=16th Symposium on Computer Architecture and High Performance Computing"

共 4419 条记录，以下是41-50 订阅

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Characterizing the Impact of Job Execution on the Occurrence of Memory Failures on a Petascale HPC System 36

Characterizing the Impact of Job Execution on the Occurrence...

引用

36th IEEE International symposium on computer architecture and high-performance computing, SBAC-PAD 2024

作者： Levy, Scott Hemmert, Josh Ferreira, Kurt B. Pedretti, Kevin Center for Computing Research Sandia National Laboratories AlbuquerqueNM United States

ISBN: (纸本)9798350356168

Characterizing the reliability of current and recent high performance (HPC) systems is critical for forecasting how future systems may behave and informing the design of fault tolerance mechanisms. Although research has been conducted to understand memory failures, there are few examples where the occurrence of memory failures is considered in the broader context of system power, temperature, and the execution of user jobs. In this paper, we combine job data with existing power, temperature, and memory failure data collected on a petascale HPC system. By focusing on periods when jobs were running on the system, we identified trends that were not evident in earlier studies of this same data. the inclusion of job data also demonstrated how user behavior can affect the occurrence of memory failures. In conjunction with this paper, we have publicly released the job data used in this paper to complement existing publicly-available data from Astra regarding power, temperature, and the occurrence of correctable memory failures. © 2024 IEEE.

关键词： fault tolerance high-performance computing memory

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Poster: Integration of Wearable and Affective computing via Abstraction and Decision Fusion architecture 25

Poster: Integration of Wearable and Affective Computing via ...

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25th IEEE International symposium on a World of Wireless, Mobile and Multimedia Networks (IEEE WoWMoM)

作者： Najafi, Mohammadreza Fallah, Mohammad K. Gorgin, Saeid Jaberipur, Ghassem Lee, Jeong-A Chosun Univ Dept Comp Engn Gwangju South Korea

ISBN: (纸本)9798350394665;9798350394672

this paper introduces an efficient emotion detection method to integrate wearable and affective computing paradigms. Our research contributes to advancing emotion detection technologies, offering potential applications in diverse domains such as healthcare, human-computer interaction, and personalized computing experiences. Our approach addresses the increasing need for real-time emotion recognition while minimizing computational demands. By leveraging low-computation techniques, we propose a novel framework that achieves high accuracy in emotion detection. Besides, advanced data abstraction methods are developed to reduce data workload keeping detection performance. Experimental results demonstrate a notable accuracy rate of 89.77%, affirming the efficacy of our proposed method.

关键词： Emotion Detection Machine Learning Computation Reduction Data Abstraction

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Conceptual and comparative analysis of application metrics in microservices 35

Conceptual and comparative analysis of application metrics i...

引用

35th IEEE International symposium on computer architecture and high performance computing (SBAC-PAD)

作者： Gulka Pulcinelli, Lucas Eduardo Pedroso, Diego Frazatto Bruschi, Sarita Mazzini Univ Sao Paulo ICMC Inst Comp Sci & Math Sao Carlos Brazil

ISBN: (纸本)9798350381603

Cloud computing represents an extensively implemented paradigm for provisioning distributed services, offering a significant degree of scalability for global applications. Nonetheless, when confronted with the necessity to scale, the system encounters monitoring challenges, as it must contend with an increased volume of requests while simultaneously accommodating fluctuating demands across various geographic regions. Aside from that, detecting errors in such a model becomes increasingly difficult, because of the many abstraction layers and interconnected microservices a cloud solution has. In that context, metrics can be used to identify errors and monitor the system's state. the substantial diversity in the types of services and the metrics themselves introduces a formidable complexity to the analysis of an entire cluster. therefore, it is important to identify the essential metrics in microservices that can be used to recognize issues or bottlenecks. In pursuit of this objective, a cloud-based solution was implemented within an Amazon Web Services Kubernetes cluster to emulate the functionality of an online retail store and an automated testing framework was made to inject errors in different parts of this application while its metrics were obtained. In that way, it was possible to identify the effects that errors have on the metrics of components in the system, rendering the monitoring of the cluster a more direct process and reducing the amount of data to be analyzed in order to identify the presence of errors in a cloud environment.

关键词： Cloud computing Chaos engineering Microservice Observability

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high performance Connected Components Accelerator for Image Processing in the Edge 20th

High Performance Connected Components Accelerator for Image ...

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20th International symposium on Applied Reconfigurable computing (ARC)

作者： Mira, Jose L. Barba, Jesus Caba, Julian de la Torre, Jose A. Rincon, Fernando Escolar, Soledad Lopez, Juan Carlos Paseo Univ Technol & Informat Syst Dept Sch Comp Sci 4 Ciudad Real Castilla La Mancha 13071 Spain

ISBN: (纸本)9783031556722;9783031556739

In image processing, a connected components algorithm is a method used to identify and label the different objects or regions present in a digital image. this algorithm can be useful for a variety of image processing tasks, such as object recognition, image segmentation, and feature extraction. this work presents the implementation of a single-pass algorithm on an FPGA-based device suitable for high-performance edge computing vision applications, the Ultra96-V2 computing board. the design and implementation of the IP core have faced challenges using the AMD-Xilinx HLS workflow and tools, which require efficient and optimized use of resources, as well as the re-engineering of the algorithm to comply with the requirements imposed by the development framework. the performance of the proposed accelerator has been thoroughly analysed using the YACCLAB benchmarking framework against a high-end and a low-end CPU. the results show an expected loss in performance due to memory and clock frequency limitations. However, concerning energy efficiency, the hardware multicore architecture outperforms the software alternatives with an improvement between two and five times, depending on the size and complexity of the images.

关键词： Connected Components high performance Edge Processing computer Vision Field Programmable Gate Arrays

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HIE-DRAM: high performance Efficient In-DRAM computing architecture for SIMD 24

HIE-DRAM: High Performance Efficient In-DRAM Computing Archi...

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24th International symposium on Quality Electronic Design (ISQED)

作者： Kabra, Mayank Prashanth, H. C. Deshpande, Kedar Rao, Madhav IIIT Bangalore Bangalore Karnataka India

ISBN: (纸本)9798350334753

In-memory and near-memory computing allows for placing the processing elements around the periphery or inside the memory blocks. Performing the computation as soon as the data is made available in the memory sub-blocks avoids the need to wait for the processor to manage the data movement. the paper focuses on a new 11 transistor (11T) computing design and a novel operation with energy savings and performance improvement when compared to the current state-of-the-art (SOTA) available single-instruction- multiple-data in-DRAM (SIMDRAM) computing. the novel 11T pass transistor design is structured to offer logical AND, OR, XNOR and its complement operations. these are sequenced to generate desired operational output with a minuscule change of 4 row circuitry that corresponds to footprint expense of 0.05% when compared to the existing DRAM architecture. Based on these logical operations, 13 scalar instructions covering arithmetic, predication, reduction, and relational function types are characterized. these scalar operations is a mix of logarithmic, quadratic, and linear functions applied on either a single or multiple operand. With respect to single-instruction- multiple-data (SIMD) topology, vector operations comprising addition, multiplication, sparse multiplication, selection, unique, reduction, and prefix summation are also realized. All these operations were compared with the current SOTA SIMDRAM architectural design to showcase profound computing time benefits and energy savings. the proposed 11T in-DRAM-compute design offers 5.18% to 50.57% improvement in computing latency and energy across 10 scalar operations, over SIMDRAM architecture. the novel high performance and efficient in-DRAM computing (HIE-DRAM) implementation is a step towards utilizing real-time in-memory vector data processing for autonomous applications.

关键词： Processing-in-Memory In-Memory-SIMD DRAM Accelerator Design computer architecture

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MetaStackVis: Visually-Assisted performance Evaluation of Metamodels 16

MetaStackVis: Visually-Assisted Performance Evaluation of Me...

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IEEE 16th Pacific Visualization symposium (IEEE PacificVis)

作者： Ploshchik, Ilya Chatzimparmpas, Angelos Kerren, Andreas Linnaeus Univ Vaxjo Sweden Linkoping Univ Linkoping Sweden

ISBN: (纸本)9798350321241

Stacking (or stacked generalization) is an ensemble learning method with one main distinctiveness from the rest: even though several base models are trained on the original data set, their predictions are further used as input data for one or more metamodels arranged in at least one extra layer. Composing a stack of models can produce high-performance outcomes, but it usually involves a trial-and-error process. therefore, our previously developed visual analytics system, StackGenVis, was mainly designed to assist users in choosing a set of top-performing and diverse models by measuring their predictive performance. However, it only employs a single logistic regression metamodel. In this paper, we investigate the impact of alternative metamodels on the performance of stacking ensembles using a novel visualization tool, called MetaStackVis. Our interactive tool helps users to visually explore different singular and pairs of metamodels according to their predictive probabilities and multiple validation metrics, as well as their ability to predict specific problematic data instances. MetaStackVis was evaluated with a usage scenario based on a medical data set and via expert interviews.

关键词： Human-centered computing Visualization Visualization systems and tools

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Verified high performance computing: the SyDPaCC Approach 16th

Verified High Performance Computing: The SyDPaCC Approach

引用

16th International Conference on Verification and Evaluation of computer and Communication Systems (VECoS)

作者： Loulergue, Frederic Ed-Dbali, Ali Univ Orleans INSA CVL LIFO EA 4022 Orleans France

ISBN: (纸本)9783031497360;9783031497377

the SYDPACC framework for the COQ proof assistant is based on a transformational approach to develop verified efficient scalable parallel functional programs from specifications. these specifications are written as inefficient (potentially with a high computational complexity) sequential programs. We obtain efficient parallel programs implemented using algorithmic skeletons that are higher-order functions implemented in parallel on distributed data structures. the output programs are constructed step-by-step by applying transformation theorems. Leveraging COQ type classes, the application of transformation theorems is partly automated. the current version of the framework is presented and exemplified on the development of a parallel program for the maximum segment sum problem. this program is experimented on a parallel machine.

关键词： program transformation scalable parallel computing functional programming interactive theorem proving

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eDRAM-OESP: A novel performance efficient in-embedded-DRAM-compute design for on-edge signal processing application 24

eDRAM-OESP: A novel performance efficient in-embedded-DRAM-c...

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24th International symposium on Quality Electronic Design (ISQED)

作者： Kabra, Mayank Prashanth, H. C. Deshpande, Kedar Rao, Madhav IIIT Bangalore Bangalore India

ISBN: (纸本)9798350334753

In-Memory-computing (IMC) architectures allow arithmetic and logical functionalities around the memory arrays to effectively use the memory bandwidth and avoid frequent data movement to the processor. As expected, the IMC architecture leads to high throughput performance and significant energy savings primarily due to less workload moving data from memory to the computing core. Embedded DRAM (eDRAM), composed of 1-transistor, 1-capacitor (1T1C) bit cell with logic block enables computing with benefits in terms of power savings and high performance, favorable for embedded computing engines. the work proposes a novel in-eDRAM-compute design employing a 1T1C eDRAM cell with the bit-serial computation that targets 3x throughput efficiency by arranging the operand bits in an interleaved manner. the interleaved eDRAM architecture enables to employ reading corresponding bits of multiple operands from the memory cells at the same time, and also allows to write back post computing in the same activate window, thereby saving on the multiple precharge and activate cycles. Additionally, the interleaved architecture allows pipelining the continuously arriving digitized signal and processes the same. the computing block in the form of a 1-bit adder with a multiplexer unit is optimized for different hardware metrics such as delay, power, and product of power-and-delay (PDP) for adopting the design per the specifications. the eDRAM-based efficient computing design is evaluated for 1-bit adder and further characterized for 8-bit, and 16-bit adders, multipliers, and 1-D convolution of varying filter sizes. the proposed design exhibited improvement in computing time by 31% for 16-bit addition and 30.6% for 8-bit addition over the existing state-of-the-art work. the bit-serial in-eDRAM-compute design achieved the best performance of 2.5 ms of computing time and 120 nJ of energy for performing a 1-D convolution operation. the in-eDRAM-compute design is a step towards designing embedded

关键词： In-memory-computing embedded DRAM Adder Multiplier Convolution Signal filtering

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Spectral-Blaze: A high-performance FFT-Based CNN Accelerator 20th

Spectral-Blaze: A High-Performance FFT-Based CNN Accelerator

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20th International symposium on Applied Reconfigurable computing (ARC)

作者： Sunny, Shine Parekkadan Das, Satyajit Indian Inst Technol IIT Palakkad Palakkad Kerala India

ISBN: (纸本)9783031556722;9783031556739

this paper presents Spectral-Blaze, a novel FFT-based CNN accelerator that effectively addresses computational and energy bottlenecks in spatial domain acceleration. the proposed architecture introduces Intra-Patch parallelization during the Hadamard product phase, which optimizes Complex MAC (CMAC) unit utilization and maintains consistent reuse patterns across multiple input feature map patches. this parallelization scheme simplifies the tiling, enabling independent selection of patch elements for efficient on-chip memory storage. Additionally, it leverages the Flex-Stationary dataflow to adaptively store tensors with high reuse opportunities in the on-chip memory, reducing the DRAM traffic. Spectral-Blaze also introduces an optimized FFT/IFFT process that integrates a modified row-column FFT, real FFT-based optimizations, and a vector-radix IFFT. the Spectral-Blaze prototype, implemented on the Zynq MPSoC (ZU7CG), demonstrates impressive performance gains, achieving a speedup of 4.98x for VGG-16 and 1.64x for AlexNet compared to baseline. the Energy-Delay Product (EDP) varies from 4.47x to 25.14x. Compared to flexible dataflow spatial accelerators, Spectral-Blaze achieves an average improvement of 8.82x over Eyeriss and 7.87x improvement over Flexflow in EDP while maintaining a comparable hardware setup. Spectral-Blaze also achieves a 4.59x reduction in MAC operations during convolution, even with VGG-16's compact filter sizes.

关键词： FFT-based convolution Tiling DNN Accelerator Intra-Patch Parallelization Flex-Stationary

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A NUMA-aware Graph Database for Hybrid Memory System 21

A NUMA-aware Graph Database for Hybrid Memory System

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21st IEEE International symposium on Parallel and Distributed Processing with Applications, 13th IEEE International Conference on Big Data and Cloud computing, 16th IEEE International Conference on Social computing and Networking and 13th International Conference on Sustainable computing and Communications, ISPA/BDCloud/SocialCom/SustainCom 2023

作者： Tan, Shaoheng Liu, Chang Li, Dingding Tang, Yong Zeng, Deze South China Normal University School of Computer Science Guangdong Guangzhou510631 China China University of Geosciences School of Computer Science Hubei Wuhan430074 China

ISBN: (纸本)9798350329223

Compared to traditional relational databases (RDBMS), specialized graph databases (GDBs) can efficiently store and process graph data in both time and space. Hence, domains like social networks often use GDBs for data management, such as representing friendships. Optane DC Persistent Memory Module (DCPMM) is a novel memory device combining byte-addressability, non-volatility, high density and superior performance. Intuitively, applying GDB on DCPMM with the Non-Uniform Memory Access (NUMA) architecture may improve I/O performance, yet the real performance may be unstable due to stacked hardware characteristics. Specifically, DCPMM exhibits serious NUMA effects and unexpected read/write asymmetry compared to DRAM. To tackle these issues, we propose a NUMA-aware graph database called NAPGDB. NAPGDB employs delegated thread pools to improve the latency of accessing remote nodes. Additionally, it categorizes read/write requests into short-running and long-running tasks, with the former being served synchronously instead of using delegated threads to improve CPU utilization. We implement NAPGDB and the experimental results show that NAPGDB can improve the remote throughput by 1.3x-1.7x compared with the multithreaded Redis with RedisGraph. © 2023 IEEE.

关键词： Graph Databases

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