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Proceedings - 16th workshop on interaction between compilers and computer architectures, interact 2012

Proceedings - 16th Workshop on Interaction Between Compilers...

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16th workshop on interaction between compilers and computer architectures, interact 2012

ISBN: (纸本)9781467326148

the proceedings contain 6 papers. the topics discussed include: doubling the number of registers on arm processors;enhancing LRU replacement via phantom associativity;MGC: multiple graph-coloring for non-volatile memory based hybrid scratchpad memory;understand and categorize dynamically dead instructions for contemporary architectures;cooperative heterogeneous computing for parallel processing on CPU/GPU hybrids;and lazy reference counting for the microgrid.

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Proceedings - Annual workshop on interaction between compilers and computer architectures, interact: Preface

Proceedings - Annual Workshop on Interaction between Compile...

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16th workshop on interaction between compilers and computer architectures, interact 2012

Welcome to the 16th workshop on interaction between compilers and computer architectures (interact-16), held on February 25, 2012, in New Orleans, Louisiana. this year, the workshop was held in conjunction with the 18... 详细信息

ISBN: (纸本)9781467326148

关键词： computer architecture

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Cooperative heterogeneous computing for parallel processing on CPU/GPU hybrids

Cooperative heterogeneous computing for parallel processing ...

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16th workshop on interaction between compilers and computer architectures, interact 2012

作者： Lee, Changmin Ro, Won W. Gaudiot, Jean-Luc School of Electrical and Electronic Engineering Yonsei University Seoul 120-749 Korea Republic of Department of Electrical Engineering and Computer Science University of California Irvine CA 92697-2625 United States

ISBN: (纸本)9781467326148

this paper presents a cooperative heterogeneous computing framework which enables the efficient utilization of available computing resources of host CPU cores for CUDA kernels, which are designed to run only on GPU. the proposed system exploits at runtime the coarse-grain thread-level parallelism across CPU and GPU, without any source recompilation. To this end, three features including a work distribution module, a transparent memory space, and a global scheduling queue are described in this paper. With a completely automatic runtime workload distribution, the proposed framework achieves speedups as high as 3.08 compared to the baseline GPU-only processing. © 2012 IEEE.

关键词： Graphics processing unit

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Doubling the number of registers on ARM processors

Doubling the number of registers on ARM processors

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16th workshop on interaction between compilers and computer architectures, interact 2012

作者： Chiang, Hsu-Hung Cheng, Huang-Jia Hwang, Yuan-Shin Department of Computer Science and Information Engineering National Taiwan University of Science and Technology Taipei 106 Taiwan

ISBN: (纸本)9781467326148

It is critical that more architectural registers are available to the compiler and programmer, as a small number of architectural registers might hinder the compiler and programmer from producing efficient code. Although modern chip manufacturing processes could easily put many registers on an ARM processor, only 16 general registers are accessible by the compiler and programmer. Doubling the number of architectural registers requires adding another bit to each register field of instructions, and hence increases code size. One approach has been developed to use the underutilized condition bits to double the number of architectural registers from 16 to 32 but maintain the width of ARM instructions. Although performance gain can generally be achieved by most of benchmark programs on a 32-register ARM, this approach would still hurt performance for programs with high ratios of instructions that can be conditionalized. therefore, a better approach would to keep the conditional execution feature even when the 4-bit condition field is used to encode the extra registers. this paper proposes to borrow the IT instruction from thumb II ISA to represent the predicates of conditionalized instructions on the 32-register ARM. GCC and SimpleScalar/ARM have been modified to handle the new instruction format and the revised IT instruction, and experimental results have shown that performance can be improved by 10.4% on average for MediaBench II benchmarks on the 32-register ARM with conditional execution. © 2012 IEEE.

关键词： ARM processors

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MGC: Multiple graph-coloring for non-volatile memory based hybrid Scratchpad Memory

MGC: Multiple graph-coloring for non-volatile memory based h...

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16th workshop on interaction between compilers and computer architectures, interact 2012

作者： Li, Qingan Zhao, Yingchao Hu, Jingtong Xue, Chun Jason Sha, Edwin He, Yanxiang Department of Computer Science City University of Hong Kong Hong Kong School of Computer Science Wuhan University China Department of Computer Science University of Texas Dallas TX United States College of Computer Science Chongqing University China

ISBN: (纸本)9781467326148

Scratchpad Memory (SPM), a software-controlled on-chip memory, has been widely used as an alternative to caches in modern embedded systems due to its energy efficiency. To further reduce the energy consumption, non-volatile memory (NVM) based hybrid SPM has been proposed recently. this paper targets the problem of allocating program variables into hybrid SPM based systems. Both an ILP formulation and a graph-coloring based algorithm are proposed. the experiments show that the proposed graph-coloring framework achieves both better memory latency and lower energy costs in comparison to previous works. © 2012 IEEE.

关键词： Energy utilization

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Understand and categorize dynamically dead instructions for contemporary architectures

Understand and categorize dynamically dead instructions for ...

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16th workshop on interaction between compilers and computer architectures, interact 2012

作者： Jantz, Marianne J. Kulkarni, Prasad A. Department of Electrical Engineering and Computer Science University of Kansas Lawrence KS United States

ISBN: (纸本)9781467326148

Instructions executed by the processor are dynamically dead if the values they produce are not used by the program. Researchers have discovered that a surprisingly large fraction of executed instructions are dynamically dead. Dynamically dead instructions (DDI) can potentially slow-down program execution and waste power. Unfortunately, although the issue of DDI is well-known, there has not been any comprehensive study to understand and explain the occurrence of DDI, evaluate its performance impact, and resolve the problem for contemporary architectures. the goals of our research are to measure the ratio of DDI and systematically characterize them for existing state-of-the-art compilers and popular architectures, and then develop compiler and/or architectural techniques to avoid their execution at runtime. In this paper, we describe our GCC-based framework to instrument binary programs to generate control-flow and data-flow (registers and memory) traces at runtime. We present the distribution and percentage of DDI in our benchmark programs. We find that for the x86 platform, our embedded systems benchmarks compiled with GCC generally contain significantly fewer DDI than those observed in earlier research for other architectures. We also describe the outcome of our manual study to analyze and categorize the instances of dead instructions in our programs into seven distinct categories. We briefly describe our plan to develop compiler and architecture based techniques to eliminate each category of DDI in future programs. We believe that a close synergy between static code generation and program execution techniques may be the most effective strategy to eliminate DDI. © 2012 IEEE.

关键词： Embedded systems

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Cooperative heterogeneous computing for parallel processing on CPU/GPU hybrids

Cooperative heterogeneous computing for parallel processing ...

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Annual workshop on interaction between compilers and computer architectures

作者： Changmin Lee Won W. Ro Jean-Luc Gaudiot School of Electrical and Electronic Engineering Yonsei University Seoul South Korea Department of Electrical Engineering and Computer Science University of California Irvine CA USA

关键词： Graphics processing unit Kernel Instruction sets Central Processing Unit Runtime Parallel processing Multicore processing

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MGC: Multiple graph-coloring for non-volatile memory based hybrid Scratchpad Memory

MGC: Multiple graph-coloring for non-volatile memory based h...

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Annual workshop on interaction between compilers and computer architectures

作者： Qingan Li Yingchao Zhao Jingtong Hu Chun Jason Xue Edwin Sha Yanxiang He School of Computer Science Wuhan University China Department of Computer Science City University of Hong Kong Hong Kong China Department of Computer Science University of Texas Dallas USA College of Computer Science Chongqing University China

关键词： Abstracts Random access memory Arrays

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Understand and categorize dynamically dead instructions for contemporary architectures

Understand and categorize dynamically dead instructions for ...

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Annual workshop on interaction between compilers and computer architectures

作者： Marianne J. Jantz Prasad A. Kulkarni Department of Electrical Engineering and Computer Science University of Kansas Lawrence KS USA

关键词： Optimization Benchmark testing Program processors Heuristic algorithms Instruments Registers computer architecture

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