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Scalable Top-K Retrieval with Sparta 20

Scalable Top-K Retrieval with Sparta

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25th acm sigplan symposium on principles and practice of parallel programming (PPoPP)

作者： Sheffi, Gali Basin, Dmitry Bortnikov, Edward Carmel, David Keidar, Idit Technion Haifa Israel Yahoo Res Haifa Israel Amazon Haifa Israel

ISBN: (纸本)9781450368186

Many big data processing applications rely on a top-k retrieval building block, which selects (or approximates) the k highest-scoring data items based on an aggregation of features. In web search, for instance, a document's score is the sum of its scores for all query terms. Top-k retrieval is often used to sift through massive data and identify a smaller subset of it for further analysis. Because it filters out the bulk of the data, it often constitutes the main performance bottleneck. Beyond the rise in data sizes, today's data processing scenarios also increase the number of features contributing to the overall score. In web search, for example, verbose queries are becoming mainstream, while state-of-the-art algorithms fail to process long queries in real-time. We present Sparta, a practical parallel algorithm that exploits multi-core hardware for fast (approximate) top-k retrieval. thanks to lightweight coordination and judicious context sharing among threads, Sparta scales both in the number of features and in the searched index size. In our web search case study on 50M documents, Sparta processes 12-term queries more than twice as fast as the state-of-the-art. On a tenfold bigger index, Sparta processes queries at the same speed, whereas the average latency of existing algorithms soars to be an order-of-magnitude larger than Sparta's.

关键词： parallel computing multi-threading performance information retrieval web search top-k search

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Well-structured futures and cache locality 14

Well-structured futures and cache locality

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2014 19th acm sigplan symposium on principles and practice of parallel programming, PPoPP 2014

作者： Herlihy, Maurice Liu, Zhiyu Computer Science Department Brown University United States

ISBN: (纸本)9781450326568

In fork-join parallelism, a sequential program is split into a directed acyclic graph of tasks linked by directed dependency edges, and the tasks are executed, possibly in parallel, in an order consistent with their dependencies. A popular and effective way to extend fork-join parallelism is to allow threads to create futures. A thread creates a future to hold the results of a computation, which may or may not be executed in parallel. that result is returned when some thread touches that future, blocking if necessary until the result is ready. Recent research has shown that while futures can, of course, enhance parallelism in a structured way, they can have a deleterious effect on cache locality. In the worst case, futures can incur Ω(PT ∞ +tT∞) deviations, which implies Ω(CPT∞+CtT∞) additional cache misses, where C is the number of cache lines, P is the number of processors, t is the number of touches, and T∞ is the computation span. Since cache locality has a large impact on software performance on modern multicores, this result is troubling. In this paper, however, we show that if futures are used in a simple, disciplined way, then the situation is much better: if each future is touched only once, either by the thread that created it, or by a later descendant of the thread that created it, then parallel executions with work stealing can incur at most O(CPT2∞ ) additional cache misses, a substantial improvement. this structured use of futures is characteristic of many (but not all) parallel applications. Copyright © 2014 acm.

关键词： parallel programming

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throughput-Oriented GPU Memory Allocation 19

Throughput-Oriented GPU Memory Allocation

引用

24th acm sigplan symposium on principles and practice of parallel programming (PPoPP)

作者： Gelado, Isaac Garland, Michael NVIDIA Santa Clara CA 95051 USA

ISBN: (纸本)9781450362252

throughput-oriented architectures, such as GPUs, can sustain three orders of magnitude more concurrent threads than multicore architectures. this level of concurrency pushes typical synchronization primitives (e.g., mutexes) over their scalability limits, creating significant performance bottlenecks in modules, such as memory allocators, that use them. In this paper, we develop concurrent programming techniques and synchronization primitives, in support of a dynamic memory allocator, that are efficient for use with very high levels of concurrency. We formulate resource allocation as a two-stage process, that decouples accounting for the number of available resources from the tracking of the available resources themselves. To facilitate the accounting stage, we introduce a novel bulk semaphore abstraction that extends traditional semaphore semantics by optimizing for the case where threads operate on the semaphore simultaneously. We also similarly design new collective synchronization primitives that enable groups of cooperating threads to enter critical sections together. Finally, we show that delegation of deferred reclamation to threads already blocked greatly improves efficiency. Using all these techniques, our throughput-oriented memory allocator delivers both high allocation rates and low memory fragmentation on modern GPUs. Our experiments demonstrate that it achieves allocation rates that are on average 16.56 times higher than the counterpart implementation in the CUDA 9 toolkit.

关键词： Concurrency Memory Allocation GPU programming

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A collection-oriented programming model for performance portability 2015

A collection-oriented programming model for performance port...

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20th acm sigplan symposium on principles and practice of parallel programming, PPoPP 2015

作者： Muralidharan, Saurav Garland, Michael Catanzaro, Bryan Sidelnik, Albert Hall, Mary University of Utah Salt Lake CityUT United States NVIDIA Corporation Santa ClaraCA United States Baidu Inc. SunnyvaleCA United States

ISBN: (纸本)9781450332057

this paper describes Surge, a collection-oriented programming model that enables programmers to compose parallel computations using nested high-level data collections and operators. Surge exposes a code generation interface, decoupled from the core computation, that enables programmers and autotuners to easily generate multiple implementations of the same computation on various parallel architectures such as multi-core CPUs and GPUs. By decoupling computations from architecture-specific implementation, programmers can target multiple architectures more easily, and generate a search space that facilitates optimization and customization for specific architectures. We express in Surge four real-world benchmarks from domains such as sparse linear-algebra and machine learning and from the same performance-portable specification, generate OpenMP and CUDA C++ implementations. Surge generates efficient, scalable code which achieves up to 1.32x speedup over handcrafted, well-optimized CUDA code.

关键词： parallel architectures

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PPDP'08 Proceedings of the 10th International acm sigplan symposium on principles and practice of Declarative programming

PPDP'08 Proceedings of the 10th International ACM SIGPLAN Sy...

引用

PPDP 2008: 10th International acm sigplan symposium on principles and practice of Declarative programming

ISBN: (纸本)9781605581170

the proceedings contain 25 papers. the topics discussed include: order-sorted dependency pairs;macros for context-free grammars;inferring precise polymorphic type dependencies in logic programs;a type system for safe memory management and its proof of correctness;programming with proofs and explicit contexts;towards execution time estimation in abstract machine-based languages;similarity-based reasoning in qualified logic programming;classifying integrity checking methods with regard to inconsistency tolerance;comprehending finite maps for algorithmic debugging of higher-order functional programs;parallel execution of multi-set constraint rewrite rules;a rewriting framework for the composition of access control policies;global difference constraint propagation for finite domain solvers;and dynamic variable elimination during propagation solving.

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A framework for practical parallel fast matrix multiplication 2015

A framework for practical parallel fast matrix multiplicatio...

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20th acm sigplan symposium on principles and practice of parallel programming, PPoPP 2015

作者： Benson, Austin R. Ballard, Grey Institute for Computational and Mathematical Engineering Stanford University StanfordCA United States Sandia National Laboratories LivermoreCA United States

ISBN: (纸本)9781450332057

Matrix multiplication is a fundamental computation in many scientific disciplines. In this paper, we show that novel fast matrix multiplication algorithms can significantly outperform vendor implementations of the classical algorithm and Strassen's fast algorithm on modest problem sizes and shapes. Furthermore, we show that the best choice of fast algorithm depends not only on the size of the matrices but also the shape. We develop a code generation tool to automatically implement multiple sequential and shared-memory parallel variants of each fast algorithm, including our novel parallelization scheme. this allows us to rapidly benchmark over 20 fast algorithms on several problem sizes. Furthermore, we discuss a number of practical implementation issues for these algorithms on shared-memory machines that can direct further research on making fast algorithms practical. Copyright 2015 acm.

关键词： Matrix algebra

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Improving parallel shear-warp volume rendering on shared address space multiprocessors 97

Improving parallel shear-warp volume rendering on shared add...

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Proceedings of the 1997 6th acm sigplan symposium on principles and practice of parallel programming

作者： Jiang, Dongming Singh, Jaswinder Pal Princeton Univ Princeton NJ United States

ISBN: (纸本)9780897919067

this paper presents a new parallel volume rendering algorithm and implementation, based on shear warp factorization, for shared address space multiprocessors. Starting from an existing parallel shear-warp renderer, we use increasingly detailed performance measurements on real machines and simulators to understand performance bottlenecks. this leads us to a new parallel implementation that substantially outperforms and out-scales the old one on a range of shared address space platforms, from bus-based centralized memory machine to hardware-coherent distributed memory machines to networks of computers connected by page-based shared virtual memory. the results demonstrate that real time volume rendering is promising on general purpose multiprocessors, and illustrate the utility of tool hierarchies in conjunction with algorithmic and application knowledge to understand memory system interactions and improve parallel algorithms.

关键词： parallel algorithms

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Poster: the Problem-Based Benchmark Suite PBBS), V2 27

Poster: The Problem-Based Benchmark Suite PBBS), V2

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27th acm sigplan symposium on principles and practice of parallel programming (PPoPP)

作者： Anderson, Daniel Blelloch, Guy E. Dhulipala, Laxman Dobson, Magdalen Sun, Yihan Carnegie Mellon Univ Pittsburgh Pittsburgh PA USA Univ Maryland Coll Park MD USA UC Riverside Riverside Riverside CA USA

ISBN: (纸本)9781450392044

the Problem-Based Benchmark Suite (PBBS) is a set of benchmark problems designed for comparing algorithms, implementations and platforms. For each problem, the suite defines the problem in terms of the input-output relationship, and supplies a set of input instances along with input generators, a default implementation, code for checking correctness or accuracy, and a timing harness. the suite makes it possible to compare different algorithms, platforms (e.g. CPU vs CPU), and implementations using different programming languages or libraries. the purpose is to better understand how well a wide variety of problems parallelize, and what techniques/algorithms are most effective. the suite was first announced in 2012 with 14 benchmark problems. Here we describe some significant updates. In particular, we have added nine new benchmarks from a mix of problems in text processing, computational geometry and machine learning. We have further optimized the default implementations;several are the fastest available for multicore CPUs, often achieving near perfect speedup on the 72 core machine we test them on. the suite now also supplies significantly larger default test instances, as well as a broader variety, with many derived from real-world data.

关键词： benchmarking parallel algorithms performance

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VEBO: A vertex- and edge-balanced ordering heuristic to load balance parallel graph processing 19

VEBO: A vertex- and edge-balanced ordering heuristic to load...

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24th acm sigplan symposium on principles and practice of parallel programming, PPoPP 2019

作者： Sun, Jiawen Vandierendonck, Hans Nikolopoulos, Dimitrios S. Queen's University of Belfast United Kingdom

ISBN: (纸本)9781450362252

this work proposes Vertex- and Edge-Balanced Ordering (VEBO): balance the number of edges and the number of unique destinations of those edges. VEBO balances edges and vertices for graphs with a power-law degree distribution, and ensures an equal degree distribution between partitions. Experimental evaluation on three shared-memory graph processing systems (Ligra, Polymer and GraphGrind) shows that VEBO achieves excellent load balance and improves performance by 1.09× over Ligra, 1.41× over Polymer and 1.65× over GraphGrind, compared to their respective partitioning algorithms, averaged across 8 algorithms and 7 graphs. VEBO improves GraphGrind performance with a speedup of 2.9× over Ligra on average. © 2019 Copyright held by the owner/author(s).

关键词： Graph theory

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Formal Verification of Practical MPI Programs

Formal Verification of Practical MPI Programs

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14th acm sigplan symposium on principles and practice of parallel programming

作者： Vo, Anh Vakkalanka, Sarvani DeLisi, Michael Gopalakrishnan, Ganesh Kirby, Robert M. thakur, Rajeev Univ Utah Sch Comp Salt Lake City UT 84112 USA Argonne Natl Lab Div Math & Comp Sci Argonne IL 60439 USA

ISBN: (纸本)9781605583976

this paper considers the problem of formal verification of MPI programs operating under a fixed test harness for safety properties without building verification models. In our approach, we directly model-check the MPI/C source code, executing its interleavings with the help of a verification scheduler. Unfortunately, the total feasible number of interleavings is exponential, and impractical to examine even for our modest goals. Our earlier publications formalized and implemented a partial order reduction approach that avoided exploring equivalent interleavings, and presented a verification tool called ISP. this paper presents algorithmic and engineering innovations to ISP, including the use of OpenMP parallelization, that now enables it to handle practical MPI programs, including: (i) ParMETIS - a widely used hypergraph partitioner, and (ii) MADRE - a Memory Aware Data Re-distribution Engine, both developed outside our group. Over these benchmarks, ISP has automatically verified up to 14K lines of MPI/C code, producing error traces of deadlocks and assertion violations within seconds.

关键词： Verification MPI Message Passing Interface distributed programming model checking dynamic partial order reduction

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