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检索条件"任意字段=17th ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming"

共 368 条记录，以下是231-240 订阅

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thread to Strand Binding of parallel Network Applications in Massive Multi-threaded Systems

Thread to Strand Binding of Parallel Network Applications in...

引用

15th acm sigplan symposium on principles and practice of parallel programming

作者： Radojkovic, Petar Cakarevic, Vladimir Verdu, Javier Pajuelo, Alex Cazorla, Francisco J. Nemirovsky, Mario Valero, Mateo Univ Politecn Cataluna E-08028 Barcelona Spain CSIC Madrid Spain

ISBN: (纸本)9781605587080

In processors with several levels of hardware resource sharing, like CMPs in which each core is an SMT, the scheduling process becomes more complex than in processors with a single level of resource sharing, such as pure-SMT or pure-CMP processors. Once the operating system selects the set of applications to simultaneously schedule on the processor (workload), each application/thread must be assigned to one of the hardware contexts (strands). We call this last scheduling step the thread to Strand Binding or TSB. In this paper, we show that the TSB impact on the performance of processors with several levels of shared resources is high. We measure a variation of up to 59% between different TSBs of real multithreaded network applications running on the UltraSPARC T2 processor which has three levels of resource sharing. In our view, this problem is going to be more acute in future multithreaded architectures comprising more cores, more contexts per core, and more levels of resource sharing. We propose a resource-sharing aware TSB algorithm (TSBSched) that significantly facilitates the problem of thread to strand binding for software-pipelined applications, representative of multithreaded network applications. Our systematic approach encapsulates both, the characteristics of multithreaded processors under the study and the structure of the software pipelined applications. Once calibrated for a given processor architecture, our proposal does not require hardware knowledge on the side of the programmer, nor extensive profiling of the application. We validate our algorithm on the UltraSPARC T2 processor running a set of real multithreaded network applications on which we report improvements of up to 46% compared to the current state-of-the-art dynamic schedulers.

关键词： Algorithms Measurement Performance Process Scheduling Simultaneous Multithreading CMT UltraSPARC T2

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Architectural Support for Cilk Computations on Many-core Architectures

Architectural Support for Cilk Computations on Many-core Arc...

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14th acm sigplan symposium on principles and practice of parallel programming

作者： Long, Guoping Fan, Dongrui Zhang, Junchao Chinese Acad Sci Inst Comp Technol Key Lab Comp Syst & Architecture Beijing 100864 Peoples R China

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Turbocharging Boosted Transactions or: How I Learnt to Stop Worrying and Love Longer Transactions

Turbocharging Boosted Transactions or: How I Learnt to Stop ...

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14th acm sigplan symposium on principles and practice of parallel programming

作者： Kulkarni, Chinmay Unsal, Osman Cristal, Adrian Ayguade, Eduard Valero, Mateo Birla Inst Technol & Sci Pilani Rajasthan India Tech Univ Catalunya Catalunya Spain

ISBN: (纸本)9781605583976

Boosted transactions offer an attractive method that enables programmers to create larger transactions that scale well and offer deadlock-free guarantees. However, as boosted transactions get larger, they become more susceptible to conflicts and aborts. We describe a linear-time algorithm to detect transactions that cannot make progress, which transactions need to be aborted, and when. the algorithm guarantees zero false positives with minimal aborts. Our proposals, as implemented in DSTM2, increase the transactional throughput of the system, often by more than 30%.

关键词： Algorithms Performance Concurrency parallel programming transactional memory deadlocks deadlock-detection

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Exploiting Global Optimizations for OpenMP Programs in the OpenUH Compiler

Exploiting Global Optimizations for OpenMP Programs in the O...

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14th acm sigplan symposium on principles and practice of parallel programming

作者： Huang, Lei Eachempati, Deepak Hervey, Marcus W. Chapman, Barbara Univ Houston Dept Comp Sci Houston TX 77004 USA

ISBN: (纸本)9781605583976

the advent of new parallel architectures has increased the need for parallel optimizing compilers to assist developers in creating efficient code. OpenUH is a state-of-the-art optimizing compiler, but it only performs a limited set of optimizations for OpenMP programs due to its conservative assumptions of shared memory programming. these limitations may prevent some OpenMP applications from being fully optimized to the extent of its sequential counterpart. this paper describes our design and implementation of a parallel data flow framework, consisting of a parallel Control Flow Graph (PCFG) and a parallel SSA (PSSA) representation in OpenUH, to model data flow for OpenMP programs. this framework enables the OpenUH compiler to perform all classical scalar optimizations for OpenMP programs, in addition to conducting OpenMP specific optimizations.

关键词： Language Performance theory Compiler Analysis OpenMP parallel SSA

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Preliminary Results on NB-FEB, a Synchronization Primitive for parallel programming

Preliminary Results on NB-FEB, a Synchronization Primitive f...

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14th acm sigplan symposium on principles and practice of parallel programming

作者： Ha, Phuong Hoai Tsigas, Philippas Anshus, Otto J. Univ Tromso N-9001 Tromso Norway Chalmers Univ Technol Gothenburg Sweden

ISBN: (纸本)9781605583976

We introduce a non-blocking full/empty bit primitive, or NB-FEB for short, as a promising synchronization primitive for parallel programming on may-core architectures. We show that the NB-FEB primitive is universal, scalable and feasible. NB-FEB, together with registers, can solve the consensus problem for an arbitrary number of processes (universality). NB-FEB is combinable, namely its memory requests to the same memory location can be combined into only one memory request, which consequently mitigates performance degradation due to synchronization "hot spots" (scalability). Since NB-FEB is a variant of the original full/empty bit that always returns a value instead of waiting for a conditional flag, it is as feasible as the original full/empty bit, which has been implemented in many computer systems (feasibility).

关键词： Algorithms Reliability theory many-core architectures non-blocking synchronization full/empty bit universal primitives combinability

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L2C2: Logic-based LSC Consistency Checking

L2C2: Logic-based LSC Consistency Checking

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11th International acm sigplan symposium on principles and practice of Declarative programming (PPDP 09)

作者： Guo, Hai-Feng Zheng, Wen Subramaniam, Mahadevan Univ Nebraska Dept Comp Sci Omaha NE 68182 USA

ISBN: (纸本)9781605585680

Live sequence charts (LSCs) have been proposed as an inter-object scenario-based specification and visual programming language for reactive systems. In this paper, we introduce a logic-based framework to check the consistency of an LSC specification. An LSC simulator has been implemented in logic programming, utilizing a memoized depth-first search strategy, to show how a reactive system in LSCs would response to a set of external event sequences. A formal notation is defined to specify external event sequences, extending the regular expression with a parallel operator and a testing control. the parallel operator allows interleaved parallel external events to be tested in LSCs simultaneously;while the testing control provides users to a new approach to specify and test certain temporal properties (e.g., CTL formula) in a form of LSC. Our framework further provides either a state transition graph or a failure trace to justify the consistency checking results.

关键词： live sequence chart (LSC) scenario-based programming PLAY-tree logic programming memoization

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Comparability Graph Coloring for Optimizing Utilization of Stream Register Files in Stream Processors

Comparability Graph Coloring for Optimizing Utilization of S...

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14th acm sigplan symposium on principles and practice of parallel programming

作者： Yang, Xuejun Wang, Li Xue, Jingling Deng, Yu Zhang, Ying UNSW Programming Languages & Compilers Grp Sch Comp Sci & Engn Sydney NSW Australia

ISBN: (纸本)9781605583976

A stream processor executes an application that has been decomposed into a sequence of kernels that operate on streams of data elements. During the execution of a kernel, all streams accessed must be communicated through the SRF (Stream Register File), a non-bypassing software-managed on-chip memory. therefore, optimizing utilization of the SRF is crucial for good performance. the key insight is that the interference graphs formed by the streams in stream applications tend to be comparability graphs or decomposable into a set of multiple comparability graphs. We present a compiler algorithm that can find optimal or near-optimal colorings in stream IGs, thereby improving SRF utilization than the First-Fit bin-packing algorithm, the best in the literature.

关键词： Algorithms Languages Performance Stream processor stream programming comparability graph coloring software-managed cache

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Serialization Sets: A Dynamic Dependence-Based parallel Execution Model

Serialization Sets: A Dynamic Dependence-Based Parallel Exec...

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14th acm sigplan symposium on principles and practice of parallel programming

作者： Allen, Matthew D. Sridharan, Srinath Sohi, Gurindar S. Univ Wisconsin Dept Comp Sci Madison WI 53706 USA

ISBN: (纸本)9781605583976

this paper proposes a new parallel execution model where programmers augment a sequential program with pieces of code called serializers that dynamically map computational operations into serialization sets of dependent operations. A runtime system executes operations in the same serialization set in program order, and may concurrently execute operations in different sets. Because serialization sets establish a logical ordering on all operations, the resulting parallel execution is predictable and deterministic. We describe the API and design of Prometheus, a C++ library that implements the serialization set abstraction through compile-time template instantiation and a runtime support library. We evaluate a set of parallel programs running on the x86_64 and SPARC-V9 instruction sets and study their performance on multi-core, symmetric multiprocessor, and ccNUMA parallel machines. By contrast with conventional parallel execution models, we find that Prometheus programs are significantly easier to write, test, and debug, and their parallel execution achieves comparable performance.

关键词： Languages Performance parallel computing runtime system serialization sets serializer

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A Comparison of programming Models for Multiprocessors with Explicitly Managed Memory Hierarchies

A Comparison of Programming Models for Multiprocessors with ...

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14th acm sigplan symposium on principles and practice of parallel programming

作者： Schneider, Scott Yeom, Jae-Seung Rose, Benjamin Linford, John C. Sandu, Adrian Nikolopoulos, Dimitrios S. Virginia Tech Dept Comp Sci Blacksburg VA 24060 USA

ISBN: (纸本)9781605583976

On multiprocessors with explicitly managed memory hierarchies (EMM), software has the responsibility of moving data in and out of fast local memories. this task can be complex and error-prone even for expert programmers. Before we can allow compilers to handle the complexity for us, we must identify the abstractions that are general enough to allow us to write applications with reasonable effort, yet specific enough to exploit the vast on-chip memory bandwidth of EMM multi-processors. To this end, we compare two programming models against hand-tuned codes on the STI Cell, paying attention to programmability and performance. the first programming model, Sequoia, abstracts the memory hierarchy as private address spaces, each corresponding to a parallel task. the second, Cellgen, is a new framework which provides OpenMP-like semantics and the abstraction of a shared address spaces divided into private and shared data. We compare three applications programmed using these models against their hand-optimized counterparts in terms of abstractions, programming complexity, and performance.

关键词： Design Languages Cell BE Explicitly Managed Memory Hierarchies programming Models

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Petascale Computing with Accelerators

Petascale Computing with Accelerators

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14th acm sigplan symposium on principles and practice of parallel programming

作者： Kistler, Michael Gunnels, John Brokenshire, Daniel Benton, Brad IBM Corp Austin TX 78758 USA IBM Corp Yorktown Hts NY 10598 USA

ISBN: (纸本)9781605583976

A trend is developing in high performance computing in which commodity processors are coupled to various types of computational accelerators. Such systems are commonly called hybrid systems. In this paper, we describe our experience developing an implementation of the Linpack benchmark for a petascale hybrid system, the LANL Roadrunner cluster built by IBM for Los Alamos National Laboratory. this system combines traditional x86-64 host processors with IBM PowerXCell (TM) 8i accelerator processors. the implementation of Linpack we developed was the first to achieve a performance result in excess of 1.0 PFLOPS, and made Roadrunner the #1 system on the Top500 list in June 2008. We describe the design and implementation of hybrid Linpack, including the special optimizations we developed for this hybrid architecture. We then present actual results for single node and multi-node executions. From this work, we conclude that it is possible to achieve high performance for certain applications on hybrid architectures when careful attention is given to efficient use of memory bandwidth, scheduling of data movement between the host and accelerator memories, and proper distribution of work between the host and accelerator processors.

关键词： Algorithms Performance Design Accelerators hybrid programming models

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