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25th international conference on field programmable logic and applications

作者： Grigore, Nicolae Bogdan Koch, Dirk Univ Manchester Manchester M13 9PL Lancs England

ISBN: (纸本)9781467381239

Finding placement locations for modules on an FPGA in a limited amount of time is a crucial task that determines the efficiency of a dynamic partially reconfigurable system. In this work, we will define a placement method based on transforming the inherent two dimensional (2D) structure of the FPGA into a one dimensional string and employing string matching. Moreover, our model is suited to compute a module placement over multiple chained reconfigurable regions. Our algorithm is based on a hybrid approach consisting of an offline precompute phase at design-time which in turn is used to speed-up module placement at run-time.

关键词： field programmable gate arrays configurability placement Runtime design year

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Facilitating Easier Access to FPGAs in the Heterogeneous Cloud Ecosystems 28

Facilitating Easier Access to FPGAs in the Heterogeneous Clo...

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28th international conference on field programmable logic and applications (FPL)

作者： Minhas, Umar Ibrahim Woods, Roger Karakonstantis, Georgios Queens Univ Belfast Belfast Antrim North Ireland

ISBN: (数字)9781538685174

ISBN: (纸本)9781538685174

With FPGAs being increasingly integrated into existing software-based heterogeneous cloud environments, novel evaluation mechanisms are required to reveal the energy performance trade-offs of accelerators (FPGAs, GPUs, etc) in high-level heterogeneous programming environments. For FPGAs, this involves also a reconsideration of scheduling policies and reconfiguration methods with an aim of integrating software based approaches as well as performance optimizations for wider workload sizes. the approaches are evaluated using various reconfiguration methodologies for a number of applications.

关键词： Task analysis field programmable gate arrays Graphics processing units Cloud computing Optimization Computational modeling throughput

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Enabling Low Impact, Rapid Debug for Highly Utilized FPGA Designs 28

Enabling Low Impact, Rapid Debug for Highly Utilized FPGA De...

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28th international conference on field programmable logic and applications (FPL)

作者： Hale, Robert Hutchings, Brad Brigham Young Univ Provo UT 84602 USA

ISBN: (数字)9781538685174

ISBN: (纸本)9781538685174

Inserting soft logic analyzers into FPGA circuits is a common way to provide signal visibility at run-time, helping users locate bugs in their designs. However, this can become infeasible for highly (70-90+%) utilized designs, which leave few logic resources or block RAMs available for internal logic analyzers. this paper presents a fast, low-impact method of enabling signal visibility in these situations using LUT-based distributed memory. Trace-buffers are inserted post-PAR allowing users to quickly change the set of observed nets. Results from routing-based experiments are presented which demonstrate that, even in highly utilized designs, many design signals can be observed with this technique.

关键词： Tools field programmable gate arrays Probes Table lookup Debugging Routing

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Defect tolerance in multiple-FPGA systems

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IEE PROCEEDINGS-COMPUTERS AND DIGITAL TECHNIQUES 2006年第3期153卷 139-145页

作者： Hyder, Z. Wawrzynek, J. Univ Calif Berkeley Berkeley CA 94720 USA

SRAM-based field programmable gate arrays (FPGAs) have an inherent capacity for defect tolerance. A simple scheme that exploits this potential in multiple-FPGA systems is prod posed. the symmetry of the system is exploited to yield a large number of possible mappings of bitstreams on FPGAs, which results in a high probability that at least one functional mapping exists. It is shown that the behaviour of a system built using a large number of defective FPGAs approaches that of the ideal defect-free system. Various interconnection topologies such as the tree, the crossbar and a hybrid form are compared.

关键词： INTEGRATED circuits COMPUTER storage devices INFORMATION storage & retrieval systems COMPUTER storage device industry SYSTEMS engineering ENGINEERING field programmable gate arrays GATE array circuits programmable logic devices DIGITAL electronics

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Demonstration of Flow-in-Cloud: A multi-FPGA system 29

Demonstration of Flow-in-Cloud: A multi-FPGA system

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29th international conference on field-programmable logic and applications (FPL)

作者： Hironaka, Kazuei Iizuka, Kensuke Ben Ahmed, Akram Ullah, M. M. Imdad Yamauchi, Yugo Sun, Yuxi Yamakura, Miho Hiruma, Aoi Amano, Hideharu Keio Univ Dept Informat & Comp Sci Yokohama Kanagawa Japan

Flow-in-Cloud(FiC) is an acceleration platform designed to make a virtual monolithic large FPGA image from a number of mid-range economical FPGAs. We will show the live demonstration of the acceleration example of FiC... 详细信息

ISBN: (纸本)9781728148847

关键词： field programmable gate arrays Switches Clocks Servers Acceleration Bandwidth Prototypes

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FISH: Linux System Calls for FPGA Accelerators 27

FISH: Linux System Calls for FPGA Accelerators

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27th international conference on field programmable logic and applications (FPL)

作者： Nam, Kevin Fort, Blair Brown, Stephen Univ Toronto ECE Dept Toronto ON Canada

ISBN: (纸本)9789090304281

this paper presents the FISH (FPGA-Initiated Software-Handled) framework which allows FPGA accelerators to make system calls to the Linux operating system in CPU-FPGA systems. A special FISH Linux kernel module running on the CPU provides a system call interface for FPGA accelerators, much like the ABI which exists for software programs. We provide a proofof-concept implementation of this framework running on the Intel Cyclone V SoC device, and show that an FPGA accelerator can seamlessly make system calls as if it were the host program. We see the FISH framework being especially useful for high-level synthesis (HLS) by making it possible to synthesize software code that contains system calls.

关键词： Fish Kernel Linux field programmable gate arrays Registers Acceleration

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On the feasibility of TERO-based true random number generator on Xilinx FPGAs 30

On the feasibility of TERO-based true random number generato...

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30th international conference on field-programmable logic and applications (FPL)

作者： Fujieda, Naoki Aichi Inst Technol Dept Elect & Elect Engn Fac Engn Toyota Aichi Japan

ISBN: (纸本)9781728199023

A True Random Number Generator (TRNG) is an essential component for security applications of FPGAs. Its requirements include small logic area, high throughput, sufficient randomness backed with a mathematical model, and feasibility - ease of implementation. this paper focuses on TRNGs based on a Transition Effect Ring Oscillator (TERO) and presents a three-path configurable TERO (TC-TERO), an improved implementation of TERO that achieves high feasibility with a minimal amount of hardware. According to the evaluation with a Xilinx Artix-7 FPGA, a TC-TERO with a 20-bit configurable parameter only required 40 LUTs. By selecting one of the promising parameters, the proposed TRNG passed AIS-31 Procedure A without post-processing and NIST SP 800-22 with a simple debiasing.

关键词： Random number generation field programmable gate arrays Transition effect ring oscillator AIS-31

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Tectogrammatical Trees and Fuzzy Natural logic in Linguistic Characterization of Dynamic Processes 17

Tectogrammatical Trees and Fuzzy Natural Logic in Linguistic...

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Joint 17th World Congress of international-Fuzzy-Systems-Association / 9th international conference on Soft Computing and Intelligent Systems (IFSA-SCIS)

作者： Novak, Vilem Univ Ostrava Inst Res & Applicat Fuzzy Modeling NSC IT4Innovat 30Dubna 22 Ostrava 70103 1 Czech Republic

ISBN: (纸本)9781509049172

this paper is a contribution to the applications of fuzzy logic in modeling of linguistic semantics. the topic of interest is description of the past course of a dynamical process that is given by data in the form of time series. We suggest to use the well developed technique of linguistic theory, the so called tectogrammatical trees using which linguists represent semantics of sentences. the core of the suggested procedure is construction of the tectogrammatical tree that is then assigned a formula of fuzzy natural logic. As the latter construes semantics of the given sentence, we can construct a model on the basis of the given data. If successful, the initial sentence can be taken as a linguistic characterization of them. In this paper we demonstrate how sentences characterizing the course of the trend of time series can be assigned the formulas of fuzzy natural logic expressing their semantics via tectogrammatical trees.

关键词： Estimation field programmable gate arrays OFDM Modulation Filtration Clocks Signal processing algorithms

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An Application-Specific field-programmable Tree Ensemble Architecture 28

An Application-Specific Field-Programmable Tree Ensemble Arc...

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28th international conference on field programmable logic and applications (FPL)

作者： Kuehn, Jan Manoli, Yiannos Univ Freiburg IMTEK Dept Microsyst Engn Freiburg Germany

ISBN: (数字)9781538685174

ISBN: (纸本)9781538685174

Supervised machine learning for data classification is increasingly implemented in hardware to be integrated close to the source of the data. the ability to update a trained machine learning model is the most important property any classification system must fulfill. this is often achieved by implementing the algorithm on reconfigurable hardware but some applications require speed, size, or power efficiency only application-specific integrated circuits (ASICs) can offer. Architectures that have proven to be very efficient on reconfigurable hardware are not always suited for custom ASIC designs. We therefore propose to integrate commonly used field-programmable technology in an application-specific architecture to allow updates of the trained model. this design pattern allows deep integration into full custom ASICs while leveraging all advantages of reconfigurable hardware.

关键词： Vegetation Integrated circuit modeling field programmable gate arrays Parallel architectures Hardware Decision trees

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Application-Specific Soft-Core Vector Processor for Advanced Driver Assistance Systems 27

Application-Specific Soft-Core Vector Processor for Advanced...

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27th international conference on field programmable logic and applications (FPL)

作者： Nolting, Stephan Giesemann, Florian Hartig, Julian Schmider, Achim Paya-Vaya, Guillermo Leibniz Univ Hannover Inst Microelect Syst Appelstr 4 D-30167 Hannover Germany

ISBN: (纸本)9789090304281

Implementing convolutional neural networks for scene labelling is a current hot topic in the field of advanced driver assistance systems. the massive computational demands under hard real-time and energy constraints can only be tackled using specialized architectures. Also, cost-effectiveness is an important factor when targeting lower quantities. In this PhD thesis, a vector processor architecture optimized for FPGA devices is proposed. Amongst other hardware mechanisms, a novel complex operand addressing mode and an intelligent DMA are used to increase perfromance. Also, a C-compiler support for creating applications is introduced.

关键词： field programmable gate arrays Random access memory Computer architecture Vector processors Advanced driver assistance systems Biological neural networks Parallel processing

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