Reliability and process variability are serious issues for FPGAs in the future. Fortunately FPGAs have the ability to reconfigure in the field and at runtime, thus providing opportunities to overcome some of these iss...
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ISBN:
(纸本)9781424419609
Reliability and process variability are serious issues for FPGAs in the future. Fortunately FPGAs have the ability to reconfigure in the field and at runtime, thus providing opportunities to overcome some of these issues. this paper provides the first comprehensive survey of fault detection methods and fault tolerance schemes specifically for FPGAs, withthe goal of laying a strong foundation for future research in this field. All methods and schemes are qualitatively compared and some particularly promising approaches highlighted.
An FPGA based trigger system for an imaging particle detector has been designed and produced. the main capabilities of the system are the recognition of the track pattern of the incoming particles, the calculation of ...
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ISBN:
(纸本)9781424403127
An FPGA based trigger system for an imaging particle detector has been designed and produced. the main capabilities of the system are the recognition of the track pattern of the incoming particles, the calculation of its stopping pixel and the time discrimination of events. the description of the implemented algorithms, the FPGA architecture, the developed hardware and the main operation results are included in this paper. the trigger system has already been installed in the FAST detector and operated during the 2005 data taking period with very satisfactory performance. therefore, this trigger system will be used in the detector for further operation in the incoming years.
In this paper we examine the feasibility of a new approach to FPGA design bitstream compression which aims to optimise placement and routing in order to minimise the distribution of configuration data in the device. W...
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ISBN:
(纸本)9781424403127
In this paper we examine the feasibility of a new approach to FPGA design bitstream compression which aims to optimise placement and routing in order to minimise the distribution of configuration data in the device. We present results from a variety of experiments which demonstrate how achievable compression ratio varies withthe design size and applied constraints. the approach proves promissing for certain designs where compression ratios up to 5 were achieved without compromising design timing.
DMA transfer between a CPU and an FPGA often becomes a bottleneck of current reconfigurable machines. the DMA transfer of the machines like SRC-6 supports streaming processing with on-board memory interleaving, but as...
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ISBN:
(纸本)9781424419609
DMA transfer between a CPU and an FPGA often becomes a bottleneck of current reconfigurable machines. the DMA transfer of the machines like SRC-6 supports streaming processing with on-board memory interleaving, but as a preprocessing of the interleaving, the CPU must reorder the data for applications with severe FPGA resource constraints. this paper empirically evaluates this overhead to reveal the trade-off point. the results show that a speedup is achieved by interleaved streaming DMA when 150KB or lower data strings are transferred.
As an alternative of adding more and more instructions to CPU cores in order to address a wide range of applications, this paper examines to use a mixed grained CPU interlay fabric to provide reconfigurable instructio...
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ISBN:
(纸本)9789090304281
As an alternative of adding more and more instructions to CPU cores in order to address a wide range of applications, this paper examines to use a mixed grained CPU interlay fabric to provide reconfigurable instruction set extensions. In detail, we are examining to replace the hardened NEON SIMD unit of an ARM Cortex-A9 with an identical sized FPGA fabric. We show that by applying a set of optimizations, we are able to emulate original applications using NEON instructions at the same hardware cost and at very little performance drop by an interlay. Moreover we are demonstrating examples where special custom instructions running on a CPU-Interlay-hybrid are substantially outperforming the original hardened CPU-NEON-system, hence making a strong case to embed reconfigurability as a beneficial feature in future processors.
Effectively exploiting the variety of computational and storage resources available in common FPGA architectures for complex applications, such as the real-time implementation of vision algorithms, is often difficult ...
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ISBN:
(纸本)9781424438914
Effectively exploiting the variety of computational and storage resources available in common FPGA architectures for complex applications, such as the real-time implementation of vision algorithms, is often difficult in standard HDL design methodologies. Higher-level design tools can enable a design to more quickly explore a range of different architectures. In this paper we apply algorithmic C-to-FPGA synthesis technology in a structured design approach and demonstrate its added value on two relevant vision processing kernels: optical flow and debayering. the impact of the proposed approach on the design time, the FPGA resource consumption and the throughput is measured.
Withthe introduction of the Stratix V family, the FPGA vendor Altera is now fully supporting partial reconfiguration in all their recent FPGA devices. A distinct feature in the Altera architecture is that reconfigura...
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ISBN:
(纸本)9782839918442
Withthe introduction of the Stratix V family, the FPGA vendor Altera is now fully supporting partial reconfiguration in all their recent FPGA devices. A distinct feature in the Altera architecture is that reconfigurable regions can be arbitrarily defined which is possible by writing a configuration mask prior to writing the actual configuration data to the FPGA fabric. In this paper, we will present details and the flow for implementing partial reconfiguration using Altera FPGAs, as well as a study on configuration bitstream sizes and configuration speeds for various resource and bounding-box aspect ratio variants. the results are used to build a partial reconfiguration controller that is featuring a lightweight but effective bitstream decompression module for greatly improving configuration speed on a DE5-net board.
Over the past few decades, the use of reconfigurable computing for aerospace applications has become increasingly common despite its sensitivity to ionizing radiation. Tools are needed to test and implement fault-miti...
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ISBN:
(纸本)9782839918442
Over the past few decades, the use of reconfigurable computing for aerospace applications has become increasingly common despite its sensitivity to ionizing radiation. Tools are needed to test and implement fault-mitigation mechanisms to increase the reliability of FPGAs in space. this paper introduces a tool called the JTAG Configuration Manager (JCM) that provides high-speed programmable access to the configuration memory of Xilinx FPGAs using the JTAG serial protocol. the JCM consists of a linux-based software library running on an embedded ARM processor paired with a hardware state machine implemented in programmablelogic. Two important uses of the JCM are configuration scrubbing and fault injection. the highspeed JTAG interface allows such operations to run at up to 60 MHz, which is several times faster than traditional JTAG FPGA configuration methods. the JCM also has access to the XADC on-chip temperature monitoring and the internal Boundary SCAN, making it useful for many testing and debugging applications.
A Virtual Private Network (VPN) encrypts and decrypts the private traffic it tunnels over a public network. Maximizing the available bandwidth is an important requirement for network applications, but the cryptographi...
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ISBN:
(纸本)9782839918442
A Virtual Private Network (VPN) encrypts and decrypts the private traffic it tunnels over a public network. Maximizing the available bandwidth is an important requirement for network applications, but the cryptographic operations add significant computational load to VPN applications, limiting the network throughput. this work presents a coprocessor designed to offer hardware acceleration for these encryption and decryption operations. the open-source SigmaVPN application is used as the base solution, and a coprocessor is designed for the parts of Networking and Cryptography library (NaCl) which underlies the cryptographic operation of SigmaVPN. the hardware-software codesign of this work is implemented on a Xilinx Zynq-7000 SoC, showing a 93% reduction in the execution time of encrypting a 1024-byte frame, and this improved the TCP and UDP communication bandwidths by a factor of 4.36 and 5.36 respectively compared to pure software solution for a 1024-byte frame.
this paper presents a field-programmable gate array (FPGA) logic synthesis technique based upon Boolean satisfiability. this paper shows how to map any Boolean function into an arbitrary programmablelogic block (PLB)...
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this paper presents a field-programmable gate array (FPGA) logic synthesis technique based upon Boolean satisfiability. this paper shows how to map any Boolean function into an arbitrary programmablelogic block (PLB) architecture without any custom decomposition techniques. the authors illustrate several useful applications of this technique by showing how this technique can be used for architecture evaluation and area optimization. When evaluating the FPGA architecture, the authors focus on the basic building block of the FPGA, which they refer to as PLB. In order to illustrate the flexibility of their evaluation framework, several unrelated PLB architectures are evaluated in an automated fashion. Furthermore, the authors show that using their technique is able to reduce FPGA resource usage by 27% on average in common subcircuits found in digital design.
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