检索结果-内蒙古大学图书馆

您好，读者！请登录

内蒙古大学图书馆

首页
概况
党建
资源
服务
科研支持
- 论文收录引用证明
- 科技查新
知识产权
档案馆
帮助

咨询与建议

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

您的常用邮箱：*

您的手机号码：*

问题描述：

当前已输入0个字，您还可以输入200个字

全部搜索
期刊论文
图书
学位论文
标准
纸本馆藏
外文资源发现
数据库导航
超星发现

高级检索

时间限定

出版年份：

文献类型

图书期刊文献学位论文多媒体

馆藏选择

电子馆藏纸本馆藏

核心期刊

全部期刊 SCI 收录期刊 SSCI 收录期刊 EI 收录期刊 CSCD 收录期刊 CSSCI 收录期刊

语言

中文英文

文献类型

期刊文献图书学位论文标准纸本馆藏

帮助

文字说明：

T=题名（书名、题名），A=作者（责任者），K=主题词，P=出版物名称，PU=出版社名称，O=机构（作者单位、学位授予单位、专利申请人），L=中图分类号，C=学科分类号，U=全部字段，Y=年（出版发行年、学位年度、标准发布年）

检索规则说明：

AND代表“并且”；OR代表“或者”；NOT代表“不包含”；(注意必须大写,运算符两边需空一格)

检索范例：

范例一：(K=图书馆学 OR K=情报学) AND A=范并思 AND Y=1982-2016
范例二：P=计算机应用与软件 AND (U=C++ OR U=Basic) NOT K=Visual AND Y=2011-2016

分类表

所选分类

>> <<

限定检索结果

文献类型

1,893 篇 会议
36 篇 期刊文献
4 册 图书

馆藏范围

1,933 篇 电子文献
0 种 纸本馆藏

日期分布

学科分类号

1,264 篇 工学
- 1,079 篇 计算机科学与技术...
- 723 篇 软件工程
- 424 篇 电气工程
- 193 篇 电子科学与技术（可...
- 70 篇 控制科学与工程
- 67 篇 信息与通信工程
- 25 篇 动力工程及工程热...
- 23 篇 建筑学
- 22 篇 机械工程
- 22 篇 仪器科学与技术
- 16 篇 生物工程
- 15 篇 土木工程
- 11 篇 核科学与技术
- 11 篇 生物医学工程（可授...
- 11 篇 安全科学与工程
- 10 篇 光学工程
- 7 篇 交通运输工程
- 6 篇 化学工程与技术
- 5 篇 农业工程
160 篇 理学
- 101 篇 数学
- 42 篇 物理学
- 19 篇 生物学
- 12 篇 系统科学
- 10 篇 统计学（可授理学、...
- 8 篇 化学
51 篇 管理学
- 39 篇 管理科学与工程(可...
- 17 篇 工商管理
- 15 篇 图书情报与档案管...
13 篇 法学
- 11 篇 社会学
9 篇 经济学
- 9 篇 应用经济学
6 篇 医学
5 篇 农学
4 篇 教育学
4 篇 军事学

主题

841 篇 field programmab...
694 篇 field programmab...
286 篇 hardware
156 篇 computer archite...
121 篇 logic gates
112 篇 table lookup
102 篇 clocks
86 篇 throughput
77 篇 routing
77 篇 random access me...
77 篇 acceleration
74 篇 software
67 篇 optimization
63 篇 delays
63 篇 kernel
53 篇 algorithm design...
52 篇 registers
52 篇 logic
51 篇 switches
46 篇 system-on-chip

机构

14 篇 univ toronto dep...
9 篇 brigham young un...
9 篇 imperial coll lo...
8 篇 department of co...
8 篇 ecole polytech f...
7 篇 univ british col...
7 篇 school of comput...
7 篇 imperial coll lo...
7 篇 tokyo inst techn...
6 篇 univ tsukuba tsu...
6 篇 university of ch...
6 篇 department of el...
6 篇 univ warwick sch...
6 篇 xilinx inc san j...
5 篇 univ manchester ...
5 篇 department of el...
5 篇 univ toronto dep...
5 篇 fudan univ state...
5 篇 swiss fed inst t...
5 篇 xilinx inc 2100 ...

作者

32 篇 luk wayne
21 篇 maruyama tsutomu
16 篇 koch dirk
13 篇 wayne luk
13 篇 wilton steven j....
12 篇 ienne paolo
11 篇 fahmy suhaib a.
11 篇 betz vaughn
10 篇 cheung peter y. ...
9 篇 vaughn betz
9 篇 constantinides g...
8 篇 prasanna viktor ...
8 篇 chow paul
8 篇 amano hideharu
8 篇 akash kumar
7 篇 kapre nachiket
7 篇 teich juergen
7 篇 alonso gustavo
7 篇 hutchings brad
7 篇 paolo ienne

语言

1,922 篇 英文
11 篇 其他
1 篇 中文

检索条件"任意字段=17th International Conference on Field Programmable Logic and Applications"

共 1933 条记录，以下是171-180 订阅

全选清除本页清除全部题录导出标记到"检索档案"

详细简洁

排序：

Line Rate programmable Packet Processing in 100Gb Networks 27

Line Rate Programmable Packet Processing in 100Gb Networks

引用

27th international conference on field programmable logic and applications (FPL)

作者： Benacek, Pavel Pus, Viktor Korenek, Jan Kekely, Michal CESNET Ale Zikova 4 Prague 16000 6 Czech Republic Netcope Technol Sochorova 3232-34 Brno 61600 Czech Republic

ISBN: (纸本)9789090304281

the P4 language provides a way to describe a custom network packet processing behavior that involves header parsing, matching and assembling modified packets. Such abstraction represents a significant step towards removing the limitation of fixed-function networking devices. Our live demonstration shows a straightforward usage of an algorithm and tool that maps a P4 program to a general architecture of FPGA-based networking device. Network traffic is received, parsed, filtered and modified by the generated circuit at the full line rate of 100 Gbps Ethernet. the results of our ongoing joint research project NFV200 show that the FPGA technology can be used to improve network flexibility without the usual burden of tedious and error-prone HDL coding.

关键词： field programmable gate arrays Protocols Pipeline processing Standards Software Tools Hardware design languages

来源：评论

学校读者我要写书评

暂无评论

Modelling delay degradation due to NBTI in FPGA Look-Up Tables 26

Modelling delay degradation due to NBTI in FPGA Look-Up Tabl...

引用

26th international conference on field-programmable logic and applications (FPL)

作者： Naouss, Mohammad Marc, Francois Univ Bordeaux IMS Lab F-33400 Talence France

ISBN: (纸本)9782839918442

field-programmable Gate Arrays (FPGAs) benefit from the most advanced CMOS technology nodes, in order to meet the increasing demands of high performance and low power digital integrated circuits. this makes them susceptible to various reliability challenges at nano-scale. In this paper, we focus on aging degradation of the Look-up table (LUT) on FPGAs. We have characterized the delay degradation of LUT depending on the duty cycle of stress vectors. We have identified also that the duty cycle affects strongly the fall and moderately the rise delay of LUT due to the NBTI aging mechanism. Furthermore, a semi-empirical model of the degradation of LUT timing due to NBTI depending on the time and the duty cycle of stress vector has been investigated in this work. this model can be used to predict the degradation of a complex circuit implemented in a FPGA, and especially the risk of timing violations due to NBTI aging.

关键词： field programmable gate arrays (FPGA)

来源：评论

学校读者我要写书评

暂无评论

An FPGA-based dynamically reconfigurable platform: From concept to realization

An FPGA-based dynamically reconfigurable platform: From conc...

引用

16th international conference on field programmable logic and applications

作者： Majer, Mateusz Univ Erlangen Nurnberg Dept Comp Sci 12 D-8520 Erlangen Germany

ISBN: (纸本)9781424403127

Dynamically reconfigurable FPGA-based systems offer a new kind of flexibility such as on-demand computing, self-adaption and self-optimization capabilities by restructuring the hardware at run-time. Using partial dynamic reconfiguration allows the main system to run uninterrupted during the reconfiguration process in addition to the reduced time for the reconfiguration process. However, existing FPCFA-based platforms are hampered by physical restrictions limiting the practicability of partial reconfiguration. this led us to the concept of the Erlangen Slot Machine architecture in order to eliminate the physical and technical constraints.

关键词： Switches field programmable gate arrays Hardware Runtime Pins Random access memory Communication switching Routing Memory management Computer science

来源：评论

学校读者我要写书评

暂无评论

A Low-Power MTJ-Based Nonvolatile FPGA Using Self-Terminated logic-In-Memory Structure 26

A Low-Power MTJ-Based Nonvolatile FPGA Using Self-Terminated...

引用

26th international conference on field-programmable logic and applications (FPL)

作者： Suzuki, Daisuke Hanyu, Takahiro Tohoku Univ Frontier Res Inst Interdisciplinary Sci Sendai Miyagi 9808578 Japan Tohoku Univ Elect Commun Res Inst Sendai Miyagi 9808577 Japan

ISBN: (纸本)9782839918442

A nonvolatile field-programmable gate array (NVF-PGA), where both magnetic tunnel junction (MTJ) devices and greedy power-saving techniques are utilized, is proposed. Because the circuit components are shared among several MTJ devices by the use of logic-in-memory (LIM) structure, the number of leakage current paths is reduced, which results in leakage power reduction during power-on. Moreover, the use of the self-termination scheme, which automatically turns off the write current immediately after the desired data is written, makes it possible to minimize power consumption during the backup operation. In fact, the proposed NVFPGA exhibits a 90 % power reduction in comparison with that of a conventional SRAM-based FPGA under typical benchmark-circuit implementations.

关键词： Tunnel junctions

来源：评论

学校读者我要写书评

暂无评论

Broken-Karatsuba multiplication and its application to Montgomery modular multiplication 27

Broken-Karatsuba multiplication and its application to Montg...

引用

27th international conference on field programmable logic and applications (FPL)

作者： Ding, Jinnan Li, Shuguo Tsinghua Univ Natl Lab Informat Sci & Technol Inst Microelect Beijing Peoples R China

ISBN: (纸本)9789090304281

Large number multiplication has always been an essential operation in cryptographic algorithms. In this paper, we propose Broken-Karatsuba multiplication by applying the non-least-positive form to represent large numbers and dig the parallelism hidden in conventional Karatsuba multiplication. Further, we modify Montgomery modular multiplication algorithm with Broken-Karatsuba multiplication to make it suitable for pipeline implementation with fewer hardware resources. Based on this modified algorithm, a 256-bit two-stage modular multiplier is constructed. there is no stall in the pipeline when performing consecutive modular multiplications and the delay of a modular multiplication is reduced significantly. Implemented on Virtex-6 FPGA platforms, our design outperforms most previous works in terms of modular multiplication latency and area-time product, which makes it suitable for server-side applications.

关键词： Algorithm design and analysis Digital signal processing Pipelines Table lookup Hardware field programmable gate arrays Clocks

来源：评论

学校读者我要写书评

暂无评论

the FOS (FPGA Operating System) Demo 29

The FOS (FPGA Operating System) Demo

引用

29th international conference on field-programmable logic and applications (FPL)

作者： Vaishnav, Anuj Khoa Dang Pham Manev, Kristiyan Koch, Dirk Univ Manchester Sch Comp Sci Manchester Lancs England

ISBN: (纸本)9781728148847

With the introduction of Zynq FPGAs that provide an ARM SoC with an attached FPGA fabric, it is possible to build complex software-centric systems that are software and hardware programmable. To harness the full potential of this approach, we developed FOS an FPGA Operating System which is built on open-source FPGA community and Xilinx vendor components. A distinct feature shown in this demo is a heterogeneous resource elastic scheduler that can dynamically and automatically adjust the allocation of tasks to hardware and software resources with respect to the present load scenario. We will also show the FOS ecosystem that allows easily implementing relocatable partially reconfigurable modules directly from RTL or HLS.

关键词： field programmable gate arrays Hardware Task analysis Runtime Operating systems Fabrics

来源：评论

学校读者我要写书评

暂无评论

FPGA INTERCONNECT DESIGN USING logicAL EFFORT

FPGA INTERCONNECT DESIGN USING LOGICAL EFFORT

引用

18th international conference on field programmable and logic applications

作者： Yu, Haile Chan, Yuk Hei Leong, Philip H. W. Chinese Univ Hong Kong Dept Comp Sci & Engn Hong Kong Hong Kong Peoples R China

ISBN: (纸本)9781424419609

logical effort (LE) is a linear technique for modelling the delay of a circuit in a technology independent manner. It offers the potential to simplify delay models for FPGAs and gain more insight into how the parameters affect the result. In this paper, the LE model will be introduced and an application to FPGA interconnect driver sizing described. Simple closed form equations are given for delay, sensitivity of delay to driver size and optimal delay. the results are shown to closely agree with Spice simulations.

关键词： field programmable gate arrays (FPGA)

来源：评论

学校读者我要写书评

暂无评论

SYNthESIS OF thE SR PROGRAMMING LANGUAGE FOR COMPLEX FPGAS

SYNTHESIS OF THE SR PROGRAMMING LANGUAGE FOR COMPLEX FPGAS

引用

19th international conference on field programmable logic and applications

作者： Gasson, Nick Audsley, Neil Univ York Dept Comp Sci York YO10 5DD N Yorkshire England

ISBN: (纸本)9781424438914

Most existing approaches to targeting high-level software to FPGAs are based on extensions to C and do not map easily to the features and characteristics of modern FPGAs. these include massive parallelism and a variety of complex IP-blocks (eg. RAMs, DSPs). In this paper we discuss a hardware implementation of SR, a software language with first class concurrency and high-level IPC. We show that the language model can be implemented efficiently on an FPGA, and that it provides a natural means to encapsulate FPGA resources. We compare against a commercial C-based synthesis tool and achieve similar resource usage using a more expressive language.

关键词： field programmable gate arrays (FPGA)

来源：评论

学校读者我要写书评

暂无评论

Automation of IP core interface generation for reconfigurable computing

Automation of IP core interface generation for reconfigurabl...

引用

16th international conference on field programmable logic and applications

作者： Guo, Zhi Mitra, Abhishek Najjar, Walid Univ Calif Riverside Dept Elect Engn Riverside CA 92521 USA Univ Calif Riverside Dept Comp Sci & Engn Riverside CA 92521 USA

ISBN: (纸本)9781424403127

Pre-designed IP cores for FPGAs represent a huge intellectual and financial wealth that must be leveraged by any high-level tool targeting reconfigurable platforms. In this paper we describe a technique that automates the generation of IP core interfaces allowing these to be used as C functions transparently from within C source codes using a reconfigurable computing compiler. We also show how this same tool can be used to support run-time reconfiguration on FPGAs by generating a common wrapper that interfaces to multiple cores.

关键词： field programmable gate arrays (FPGA)

来源：评论

学校读者我要写书评

暂无评论

In-Network Online Data Analytics with FPGAs 27

In-Network Online Data Analytics with FPGAs

引用

27th international conference on field programmable logic and applications (FPL)

作者： Cooke, Ryan Fahmy, Suhaib A. Univ Warwick Sch Engn Coventry W Midlands England

ISBN: (纸本)9789090304281

the growth of sensor technology, communication systems and computation have led to vast quantities of data being available for relevant parties to utilise. applications such as the monitoring and analysis of industrial equipment, smart surveillance, and fraud detection rely on the ‘real-time’ analysis of time sensitive data gathered from distributed sources. A variety of processing tasks, such as filtering, aggregation, machine learning algorithms, or other transformations to be carried out on this data in order to extract value from it. Centralised computation strategies are often deployed in these scenarios, with the majority of the data being forwarded though the network to a datacenter environment, typically due to the lack of required computational or storage resources at the leaves of the network, and data from other sources or historical data being required. this approach has also traditionally been viewed as more scalable, as resources can be augmented through the addition of extra compute hardware and cloud services.

关键词： field programmable gate arrays Hardware Computational modeling Drones Bandwidth Real-time systems

来源：评论

学校读者我要写书评

暂无评论

没有更多数据了...

全选清除本页清除全部题录导出标记到“检索档案”

共194页 << < 14 15 16 17 18 19 20 21 22 23 > >>

检索报告对象比较合并检索0

隐藏清空

合并搜索

回到顶部

执行限定条件

内容：

评分：

请选择保存的检索档案：

请选择收藏分类：

订阅名称：

通借通还

温馨提示：

图书名称：

借书校区：

取书校区：

手机号码：

邮箱地址：

一卡通帐号：

电话和邮箱必须正确填写，我们会与您联系确认。

联系人：

所在院系：

联系邮箱：

联系电话：

内蒙古自治区呼和浩特市赛罕区大学西街235号邮编: 010021

建议与咨询 留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案： 新增检索档案 确定 取消

请选择收藏分类： 新增自定义分类 确定 取消

通借通还

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

请选择保存的检索档案：

请选择收藏分类：