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检索条件"任意字段=17th International Conference on Field Programmable Logic and Applications"

共 1932 条记录，以下是181-190 订阅

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A Demo of FPGA Aggressive Voltage Downscaling: Power and Reliability Tradeoffs 28

A Demo of FPGA Aggressive Voltage Downscaling: Power and Rel...

引用

28th international conference on field programmable logic and applications (FPL)

作者： Salami, Behzad Unsal, Osman Cristal, Adrian BSC Barcelona Spain UPC Barcelona Spain

ISBN: (数字)9781538685174

ISBN: (纸本)9781538685174

the power consumption of digital circuits, e.g., field programmable Gate Arrays (FPGAs), is directly related to their operating supply voltages. On the other hand, usually, chip vendors introduce a conservative voltage guardband below the standard nominal level to ensure the correct functionality of the design in worst-case process and environmental scenarios. For instance, this voltage guardband is empirically measured to be 12%, 20%, and 16% of the nominal level in commercial CPUs [1], Graphics Processing Units (GPUs) [2], and Dynamic RAMs (DRAMs) [3], respectively. However, in many real-world applications, this guardband is extremely conservative and eliminating it can result in significant power savings without any overhead. Motivated by these studies, we aim to extend the undevolting technique to commercial FPGAs. Toward this goal, we will practically demonstrate the voltage guardband for a representative Xilinx FPGA, with a preliminary concentration on on-chip memories, or Block RAMs (BRAMs).

关键词： field programmable gate arrays Random access memory Voltage control Reliability Voltage measurement System-on-chip Circuit faults

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Revisiting FPGA Implementation of Montgomery Multiplier in Redundant Number System for Efficient ECG applications in GF(p) 28

Revisiting FPGA Implementation of Montgomery Multiplier in R...

引用

28th international conference on field programmable logic and applications (FPL)

作者： Roy, Debapriya Basu Mukhopadhyay, Debdeep Indian Inst Technol Kharagpur Dept Comp Sci & Engn Kharagpur W Bengal India

ISBN: (数字)9781538685174

ISBN: (纸本)9781538685174

the fast implementations of ECC in GF(p) are generally implemented using specialized prime field, and henceforth, they are dependent on the structure of the prime. But, these implementations cannot be ported to generic curves which do not support such prime structures. Such generic curves are often used in various crypto-applications like pairing and post quantum secure supersingular isogeny based key exchange. In those cases, modular multiplication is executed through Montgomery multiplier which is slower compared to modular multiplication using specialized primes. this work aims to reduce the speed gap between Montgomery multiplication and modular multiplication in specialized prime field by presenting an efficient implementation of Montgomery multiplier on FPGA using the redundant number system.

关键词： Montgomery multiplier Redundant number system ECC

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A congestion driven placement algorithm for FPGA synthesis

A congestion driven placement algorithm for FPGA synthesis

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16th international conference on field programmable logic and applications

作者： Zhuo, Yue Li, Hao Mohanty, Saraju P. Univ N Texas Dept Comp Sci & Engn POB 311366 Denton TX 76203 USA

ISBN: (纸本)9781424403127

We introduce a new congestion driven placement algorithm for FPGAs in which the overlapping effect of bounding boxes is taken into consideration. Experimental results show that compared with the linear congestion method [1] used in the state-of-the-art FPGA place and route package VPR [2], our algorithm achieves channel width reduction on 70% of the 20 largest MCNC benchmark circuits (10.1% on average) while keeping the channel width of the remaining 30% benchmarks unchanged. A distinct feature of our algorithm is that the critical path delay is not elongated on average, and in most cases reduced.

关键词： field programmable gate arrays (FPGA)

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FPGA based imaging particle detector trigger system

FPGA based imaging particle detector trigger system

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16th international conference on field programmable logic and applications

作者： Martinez, Gustavo Marin, Jesus Willmott, Carlos Elect & Sensores Ciemat Avda Complutense 22 Madrid 28040 Spain

ISBN: (纸本)9781424403127

An FPGA based trigger system for an imaging particle detector has been designed and produced. the main capabilities of the system are the recognition of the track pattern of the incoming particles, the calculation of its stopping pixel and the time discrimination of events. the description of the implemented algorithms, the FPGA architecture, the developed hardware and the main operation results are included in this paper. the trigger system has already been installed in the FAST detector and operated during the 2005 data taking period with very satisfactory performance. therefore, this trigger system will be used in the detector for further operation in the incoming years.

关键词： field programmable gate arrays (FPGA)

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A high speed, low memory FPGA based LDPC decoder architecture for quasi-cyclic LDPC codes

A high speed, low memory FPGA based LDPC decoder architectur...

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16th international conference on field programmable logic and applications

作者： Saunders, Paul Fagan, Anthony D. Univ Coll Dublin DSP Res Lab Sch Elect Elect & Mech Engn Dublin 2 Ireland

ISBN: (纸本)9781424403127

We propose a novel, high speed, low memory fully programable FPGA decoder architecture to decode quasi-cyclic LDPC codes. By performing optimizations at the code construction, algorithmic and architecture levels we are able to achieve significant throughput and memory storage advantages over current FPGA decoder implementations. Our decoder employs the modified turbo decoding algorithm, to achieve a decoding throughput of 223Mbps for a framed length of 3200 bits whilst only consuming 71Kb of memory,using a Xilinx Virtex-4 architecture.

关键词： field programmable gate arrays (FPGA)

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In-field Vulnerability Analysis of Hardware-Accelerated Computer Vision applications 25

In-Field Vulnerability Analysis of Hardware-Accelerated Comp...

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25th international conference on field programmable logic and applications

作者： Chadjiminas, I. Kyrkou, C. theocharides, T. Michael, M. K. Ttofis, C. Univ Cyprus KIOS Res Ctr Intelligent Syst & Networks Dept Elect & Comp Engn Nicosia Cyprus ACC Innovat Ltd Nicosia Cyprus

ISBN: (纸本)9781467381239

In this paper, we propose an FPGA-based emulation framework that can provide dynamic vulnerability analysis for hardware-accelerated computer vision applications. the framework can be integrated alongside the targeted application, to allow for run-time, in-field, dynamically adjusted vulnerability analysis in real-world conditions, taking into consideration the non-deterministic parameters of the computer vision algorithm computations. We evaluate the proposed framework in real-time using an FPGA platform, for an obstacle avoidance (OA) computer vision application and its disparity estimation kernel to study the impact of Single-Event Upsets (SEUs).

关键词： Approximate Computing FPGA Single Event Upsets Intermittent Faults Transient Faults Computer Vision Reliability and Vulnerability Analysis

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DPA RESISTANCE FOR LIGHT-WEIGHT IMPLEMENTATIONS OF CRYPTOGRAPHIC ALGORIthMS ON FPGAS

DPA RESISTANCE FOR LIGHT-WEIGHT IMPLEMENTATIONS OF CRYPTOGRA...

引用

19th international conference on field programmable logic and applications

作者： Velegalati, Rajesh Kaps, Jens-Peter George Mason Univ Volgenau Sch IT&E Fairfax VA 22030 USA

ISBN: (纸本)9781424438914

Recent advances in field programmable Gate Array (FPGA) technology are bound to make FPGAs a popular platform for battery powered devices. Many applications of such devices are mission critical and require the use of cryptographic algorithms to provide the desired security. However, Differential Power Analysis (DPA) attacks pose a sever threat against otherwise secure cryptographic implementations. Current techniques to defend against DPA attacks such as Dynamic Differential logic (DDL) lead to an increase in area consumption of factor five or more. In this paper we show that moderate security against DPA attacks can be achieved for FPGAs using DDL resulting in an area increase of not much more than a factor two over standard FPGA implementations. Our design flow requires only FPGA design tools and some scripts.

关键词： field programmable gate arrays (FPGA)

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Micro-coded datapaths: Populating the space between finite state machine and processor

Micro-coded datapaths: Populating the space between finite s...

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16th international conference on field programmable logic and applications

作者： Kulkarni, Chidamber Brebner, Gordon Xilinx Inc San Jose CA USA

ISBN: (纸本)9781424403127

Domain-specific design flows can enable an efficient path to implementation, as well as making the design process intuitive and the designs reusable. When targeting FPGAs, there are few techniques in high level synthesis that enable thorough exploration of the inherent flexibility of the FPGA fabric as an implementation medium. In this paper, we propose a new methodology, based on micro-coded data paths, that enables design space exploration of processing engine architectures implemented in programmable logic that range from a fixed finite state machine to a soft processor. As a use case, these processing engines can be embedded within programmable logic threads that are used to carry out network packet processing. We demonstrate the application of this methodology on a network address translation application, and show that micro-coded data paths indeed enable both human designers and automated tools to explore the design space in a structured way, thus exploiting the full potential of the FPGA technology.

关键词： field programmable gate arrays (FPGA)

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Network Intrusion Detection Using Neural Networks on FPGA SoCs 29

Network Intrusion Detection Using Neural Networks on FPGA So...

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29th international conference on field-programmable logic and applications (FPL)

作者： Ioannou, Lenos Fahmy, Suhaib A. Univ Warwick Sch Engn Coventry W Midlands England

ISBN: (纸本)9781728148847

Network security is increasing in importance as systems become more interconnected. Much research has been conducted on large appliances for network security, but these do not scale well to lightweight systems such as those used in the Internet of things (IoT). Meanwhile, the low power processors used in IoT devices do not have the required performance for detailed packet analysis. We present an approach for network intrusion detection using neural networks, implemented on FPGA SoC devices that can achieve the required performance on embedded systems. the design is flexible, allowing model updates in order to adapt to emerging attacks.

关键词： Artificial neural networks Feature extraction Security Training field programmable gate arrays Internet of things

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Placement Strategies for 2.5D FPGA Fabric Architectures 28

Placement Strategies for 2.5D FPGA Fabric Architectures

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28th international conference on field programmable logic and applications (FPL)

作者： Ravishankar, Chirag Gaitonde, Dinesh Bauer, Trevor Xilinx Inc 3100 Logic Dr Longmont CO 80503 USA Xilinx Inc 2100 Logic Dr San Jose CA USA

ISBN: (数字)9781538685174

ISBN: (纸本)9781538685174

FPGAs take advantage of 2.5D stacking technology to manufacture large capacity and high performance heterogenous devices at reasonable costs. EDA tools need to be aware of and exploit physical characteristics of such devices, for example the reduced connection count between SLRs, the infrequency of SLL channel occurence in the fabric, and the aspect ratios of individual SLRs. We implement a partition driven placer to explore various EDA options to take advantage of architectural features in 2.5D FPGAs. We improve the routability of designs by optimizing the placer for discrete SLL channels and reduced connection counts. We propose a cut schedule for the partitioner to orient the placement with awareness of the aspect ratio of SLRs to improve track demands within each SLR.

关键词： field programmable gate arrays Routing Stacking Wires Fabrics Complexity theory Heating systems

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