检索结果-内蒙古大学图书馆

25th international conference on field programmable logic and applications

作者： Panjkov, Zdravko Wasserbauer, Andreas Ostermann, Timm Hagelauer, Richard Intel Mobile Commun Danube Mobile Commun Engn Linz Austria Johannes Kepler Univ Linz Inst Integrated Circuits Linz Austria

ISBN: (纸本)9781467381239

In the modern verification environment an FPGA-based prototyping has become an important part of the whole verification flow. the ability to simulate real time application in more realistic speeds allows much higher coverage than traditional HDL logic simulators. the main disadvantage of FPGA prototyping is inability to inspect and observe internal FPGA signals. Currently there are two traditional solutions for this problem. the first solution is using embedded trace-buffers to record a subset of internal signals and the second solution captures a snapshot of the current FPGA state. Both of these techniques have certain benefits and shortcomings. In this paper, we present an idea of merging these two techniques into a new hybrid approach. Using this idea we created a hybrid circuit and during our experiments showed that it preserves all good sides from both traditional approaches.

关键词： Hybrid Circuit Device Component field programmable gate arrays debugger Snapshots PROBLEM SOLUTION international Data Encryption Algorithm real-time application program PROTOTYPE

来源：评论

学校读者我要写书评

暂无评论

INCREASING STABILITY AND DISTINGUISHABILITY OF thE DIGITAL FINGERPRINT IN FPGAS thROUGH INPUT WORD ANALYSIS

INCREASING STABILITY AND DISTINGUISHABILITY OF THE DIGITAL F...

引用

19th international conference on field programmable logic and applications

作者： Patel, Hiren Kim, Yong McDonald, J. Todd Starman, LaVern USAF AF Res Lab 1940 Allbrook Dr Wright Patterson AFB OH 45433 USA Air Force Inst Technol Wright Patterson AFB OH 45433 USA

ISBN: (纸本)9781424438914

field programmable Gate Arrays (FPGAs) have become increasingly popular in circuit development due to their rapid development times and low costs. With their increased use, the need to protect their Intellectual Property (IP) becomes more urgent. the digital fingerprint accomplishes this by creating a unique identification (ID) for each FPGA. In this research, we propose methods to dramatically increase the stability and robustness of the digital fingerprint ID by the proper choice of input sequences. We also show that by properly choosing the input word, we can significantly increase the DF resistance to operating temperature changes.

关键词： field programmable gate arrays (FPGA)

来源：评论

学校读者我要写书评

暂无评论

Adaptive FPGAS: High-level architecture and a synthesis method

Adaptive FPGAS: High-level architecture and a synthesis meth...

引用

16th international conference on field programmable logic and applications

作者： Manohararajah, Valavan Brown, Stephen D. Vranesic, Zvonko G. Univ Toronto Dept Elect & Comp Engn 100 Coll St Toronto ON M4X 1K9 Canada

ISBN: (纸本)9781424403127

this paper presents preliminary work exploring adaptive field programmable gate arrays (AFPGAs). An AFPGA is adaptative in the sense that the functionality of subcircuits placed on the chip can change in response to changes observed on certain control signals. We describe the high-level architecture which adds additional control logic and SRAM bits to a traditional FPGA to produce an AFPGA. We also describe a synthesis method that identifies and resynthesizes mutually exclusive pieces of logic so that they may share the resources available in an AFPGA. the architectural feature and its associated synthesis method helps reduce circuit size by 28% on average and up to 40% on select circuits.

关键词： field programmable gate arrays (FPGA)

来源：评论

学校读者我要写书评

暂无评论

Compact Dual Block AES core on FPGA for CCM Protocol 25

Compact Dual Block AES core on FPGA for CCM Protocol

引用

25th international conference on field programmable logic and applications

作者： Resende, Joao Carlos Chaves, Ricardo Univ Lisbon Inst Super Tecn INESC ID Rua Alves Redol 9 P-1000029 Lisbon Portugal

ISBN: (纸本)9781467381239

this paper presents a compact and FPGA based implementation of the AES encryption standard, specifically designed for processing two independent 128-bit input blocks in feedback modes. this configuration is particularly focused on the Counter with CBC-MAC Protocol, but can also be adapted to other AES based encryption-authentication protocols requiring the processing of two independent data streams. Most of the state of the art solutions implementing CCMP consider large datapaths, sometimes with separated encryption datapaths for the different data streams, leading to low resource efficiency. the work herein proposed suggests that with adequate FPGA component usage and with proper data scheduling a very compact and efficient dual AES core can be derived particularly on FPGAs. Overall, the proposed structure allows for a throughput of 1.7Gbps while achieving a throughput/Slice efficiency of 24.22 Mbps/Slice, 47% higher than the existing related state of the art.

关键词： field programmable gate arrays (FPGA)

来源：评论

学校读者我要写书评

暂无评论

Generating FPGA Accelerators for Chemical Similarity Assessment 25

Generating FPGA Accelerators for Chemical Similarity Assessm...

引用

25th international conference on field programmable logic and applications

作者： Alachiotis, Nikolaos Carnegie Mellon Univ Dept Elect & Comp Engn Pittsburgh PA 15217 USA

ISBN: (纸本)9781467381239

Numerical measures of similarity/distance between objects represented by binary vectors are common in a wide range of disciplines. Searching in large-scale chemical databases requires billions of comparisons between molecules that are represented by binary fingerprints to capture the atomic structure. the performance bottleneck here is the enumeration of set bits in vectors (population count). Due to the discrete representation, similarity measures between binary fingerprints should fit well to FPGAs. We present an architecture to accelerate binary similarity assessment, evaluate various design points, and compare performance to highly optimized CPU and GPU implementations. We implement an RTL generation software, SimGenRTL, to generate accelerators of various sizes based on the proposed architecture. We find that accelerators with fewer and wider population counters allow better distribution of the hardware resources, outperforming significantly accelerators with more and narrower bit-enumeration components. SimGenRTL is available for download to allow rapid design space exploration of the computational core ahead of a full custom system implementation.

关键词： field programmable gate arrays (FPGA)

来源：评论

学校读者我要写书评

暂无评论

Synthesizable FPGA Fabrics Targetable by the Verilog-to-Routing (VTR) CAD Flow 25

Synthesizable FPGA Fabrics Targetable by the Verilog-to-Rout...

引用

25th international conference on field programmable logic and applications

作者： Kim, Jin Hee Anderson, Jason H. Univ Toronto Dept Elect & Comp Engn Toronto ON Canada

ISBN: (纸本)9781467381239

We consider implementing FPGAs using a standard cell design methodology, and present a framework for the automated generation of synthesizable FPGA fabrics. the open-source Verilog-to-Routing (VTR) FPGA architecture evaluation framework [1] is extended to generate synthesizable Verilog for its in-memory FPGA architectural device model. the Verilog can be synthesized into standard cells, placed and routed using an ASIC design flow. A second extension to VTR generates a configuration bitstream for the FPGA;that is, the bitstream configures the FPGA to realize a user-provided placed and routed design. the proposed framework and methodology opens the door to silicon implementation of a wide range of VTR-modelled FPGA fabrics. In an experimental study, area and timing-optimized FPGA implementations in 65 nm TSMC standard cells are compared with a 65 nm Altera commercial FPGA.

关键词： field programmable gate arrays (FPGA)

来源：评论

学校读者我要写书评

暂无评论

Dynamic Bitwidth Assignment for Efficient Dot Products 27

Dynamic Bitwidth Assignment for Efficient Dot Products

引用

27th international conference on field programmable logic and applications (FPL)

作者： Schmidt, Simon Joel Boland, David Monash Univ Dept Elect & Comp Syst Engn Clayton Vic Australia Univ Sydney Sch Elect & Informat Engn Sydney NSW Australia

ISBN: (纸本)9789090304281

the benefits of customising the precision throughout an FPGA design according to a design tolerance are well known. However, customising the precision of a design at run-time has the potential for an even greater performance impact. In this paper, we add the ability to dynamically choose the internal precision of a datapath. this enables a result that is at least as accurate as the worst-case under standard precisions, whilst internally operating at a lower precision. We demonstrate this technique on fused floating-point dot-product circuits. We show that for circuits with inputs that have a wide dynamic range, we can see substantial resource savings. We provide examples with savings of up to 75% of the DSPs and 16% of the ALMs over an optimised fused dot-product design.

关键词： Multiplexing Random access memory Algorithm design and analysis Adders Clocks field programmable gate arrays Hardware

来源：评论

学校读者我要写书评

暂无评论

Fast FPGA System for Microarchitecture Optimization on Synthesizable Modern Processor Design 25

Fast FPGA System for Microarchitecture Optimization on Synth...

引用

25th international conference on field programmable logic and applications

作者： Huang, Libo Wang, Yongwen Dou, Qiang Zhang, Chengyi Sun, Caixia Xu, Chao Natl Univ Def Technol Sch Comp Changsha 410073 Hunan Peoples R China

ISBN: (纸本)9781467381239

Microarchitecture optimization for processor design is a must to achieve target system performance. Provided the register transfer level (RTL) model in real chip design, this paper proposes MOFPGA system, which uses field programmable gate array (FPGA) prototyping as an effective method for fine-grain microarchitecture optimization. It is a fast, reconfigurable, and visible platform with zero impact on the performance of the monitored processor. MOFPGA implements a complete computing platform equipped with a modern out-of-order processor and is able to achieve 60 MHz processor frequency. Besides general FPGA implementation techniques such as multi-port SRAM design and gate-clock conversion, extensive optimization efforts are done to improve the FPGA performance of mapping such a large core. To our knowledge, MOFPGA is the first published FPGA system that implements a modern out-of-order processor running at such high frequency and can report the real SPEC CPU2000 evaluation results.

关键词： field programmable gate arrays (FPGA)

来源：评论

学校读者我要写书评

暂无评论

An FPGA Hardware Implementation Approach for a Phylogenetic Tree Reconstruction Algorithm with Incremental Tree Optimization 27

An FPGA Hardware Implementation Approach for a Phylogenetic ...

引用

27th international conference on field programmable logic and applications (FPL)

作者： Block, Henry Maruyama, Tsutomu Univ Tsukuba Syst & Informat Engn 1-1-1 Ten Ou Ddai Tsukuba Ibaraki 3058573 Japan

ISBN: (纸本)9789090304281

In this paper, we present an FPGA hardware implementation approach for a phylogenetic tree reconstruction with maximum parsimony algorithm. the algorithm, based on stochastic local search, uses the Indirect Calculation of Tree Lengths and the Incremental Tree Optimization methods. We evaluate and compare our new approach against previous hardware approaches, and against TNT, the fastest available parsimony program. We make this comparison for eight real-world biological datasets. We obtain acceleration rates per tree between 2.60 and 4.68 against a previous approach that does not use incremental optimization;between 2.19 and 4.05 against a previous approach that uses an alternative second-pass optimization;and, between 2.66 and 31.94 against TNT. Our approach is not only faster, but it does not use additional memories during the incremental optimization, as it is the case for a software approach.

关键词： Hardware Phylogeny field programmable gate arrays Optimization methods Acceleration DNA

来源：评论

学校读者我要写书评

暂无评论

Non-volatile run-time field-programmable gate arrays structures using thermally assisted switching magnetic random access memories

引用

IET COMPUTERS AND DIGITAL TECHNIQUES 2010年第3期4卷 211-226页

作者： Guillemenet, Y. Torres, L. Sassatelli, G. Univ Montpellier 2 LIRMM CNRS UMR F-34392 Montpellier 5 France

this study describes the integration of thermally assisted switching magnetic random access memories (TAS-MRAMs) in field-programmable gate array (FPGA) design. the non-volatility is achieved through the use of magnetic tunnelling junctions (MTJs) in an MRAM cell. A TAS scheme is used to write data in the MTJ device, which helps to reduce power consumption during a write operation in comparison with the conventional writing scheme used in MTJ devices. Furthermore, the non-volatility allows reducing both power consumption and configuration time required at each power-up of the circuit in comparison with classical static random access memory-based FPGAs. An innovative architecture furthermore provides run-time reconfigurable (RTR) support at minimum area overhead. A RTR FPGA element using TAS-MRAM allows dynamic reconfiguration mechanisms, while featuring simple design architecture.

关键词： MRAM devices logic circuits nonvolatility Digital circuit design, modelling and testing field programmable gate arrays logic design methods run time reconfigurable support switching magnetic random access memories logic design field programmable gate arrays structures Storage on stationary magnetic media magnetic tunnelling logic and switching circuits magnetic tunnelling junctions MRAM cell Magneto-acoustic, magnetoresistive, magnetostrictive and magnetostatic wave devices

来源：评论

学校读者我要写书评

暂无评论

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案：

请选择收藏分类：

通借通还

建议与咨询 留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案： 新增检索档案 确定 取消

请选择收藏分类： 新增自定义分类 确定 取消

通借通还

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

请选择保存的检索档案：

请选择收藏分类：