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18th international conference on field programmable and logic applications

作者： Colacicco, Immacolata Marchiori, Giacomo Tripiccione, Raffaele Univ Ferrara Dipartimento Fis I-44100 Ferrara Italy

ISBN: (纸本)9781424419609

We describe the hardware platform that will be used to run several demonstrator applications within the EU-funded hArtes project. hArtes' main goal is to support, with appropriate tools, the development of complex applications on heterogeneous and reconfigurable systems. Our platform provides a number of heterogeneous computing sub-systems, such as DSPs, general-purpose CPUs and configurable elements (in the shape of FPGAs). the envisaged applications are mainly in the audio realm, so support for high-quality audio I/O is also present. FPGAs play a dual role: i) they support I/O functions for audio streaming, moving audio signals from/to main memory with full hardware support;ii) tightly coupled to traditional processors, they make up the reconfigurable processing core within the system. this paper describes the architecture and the first implementation of the platform.

关键词： field programmable gate arrays (FPGA)

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Memory Efficient and High Performance Key-value Store on FPGA Using Cuckoo Hashing 26

Memory Efficient and High Performance Key-value Store on FPG...

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26th international conference on field-programmable logic and applications (FPL)

作者： Liang, Wei Yin, Wenbo Kang, Ping Wang, Lingli Fudan Univ State Key Lab ASIC & Syst Shanghai Peoples R China

ISBN: (纸本)9782839918442

Key-value stores (KVS) become critical in many applications because of the data explosion recently. there is a strong demand to improve the throughput and reduce the latency for KVS. FPGA-based parallel architecture can bring excellent performance and power efficiency. Cuckoo hashing has proven to be an efficient approach to implement KVS with good memory utilization and constant worst case access time. In this paper, an FPGA-based KVS implementation is proposed based on Cuckoo hashing, with a decoupled storage to achieve 81.7% memory utilization, and a pipeline scheme to achieve high performance. the latency of insert, search and delete operations is only 40 ns. And the throughput for search and delete can be 200 million requests per second (MRPS) which is 5x faster than [1]. Even when the load factor becomes 0.9, the throughput for insert can still achieve 147 MRPS.

关键词： field programmable gate arrays (FPGA)

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Invited paper: Enhanced architectures, design methodologies and cad tools for dynamic reconfiguration of Xilinx FPGAS

Invited paper: Enhanced architectures, design methodologies ...

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16th international conference on field programmable logic and applications

作者： Lysaght, Patrick Blodget, Brandon Mason, Jeff Young, Jay Bridgford, Brendan Xilinx Res Labs San Jose CA 95124 USA Xilinx Longmont CO 80503 USA

ISBN: (纸本)9781424403127

We describe architectural enhancements to Xilinx FPGAs that provide better support for the creation of dynamically reconfigurable designs. these are augmented by a new design methodology that uses pre-routed IP cores for communication between static and dynamic modules and permits static designs to route through regions otherwise reserved. for dynamic modules. A new CAD tool flow to automate the methodology is also presented. the new tools initially target the Virtex-II, Virtex-II Pro and Virtex-4 families and are derived from Yjlinx's commercial CAD tools.

关键词： field programmable gate arrays (FPGA)

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TAIGA: A NEW RISC-V SOFT-PROCESSOR FRAMEWORK ENABLING HIGH PERFORMANCE CPU ARCHITECTURAL FEATURES 27

TAIGA: A NEW RISC-V SOFT-PROCESSOR FRAMEWORK ENABLING HIGH P...

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27th international conference on field programmable logic and applications (FPL)

作者： Matthews, Eric Shannon, Lesley Simon Fraser Univ Sch Engn Sci Burnaby BC Canada

ISBN: (纸本)9789090304281

Recently, there has been an increased focus on integration of reconfigurable fabric with modern processors. However, existing soft-processors are optimized to leverage older FPGA fabrics, focus primarily on resource minimization and have fixed-pipeline designs that limit the scope for tightly integrated hardware accelerators. In this work, we present Taiga: a RISC-V, 32-bit, soft-processor architecture supporting the RISC-V Multiply/Divide and Atomic operations extensions (RV32IMA) designed to support Linux-based shared-memory systems. the processor design is highly configurable and features a standardized interface for functional units allowing for ease of integration of new functional units. Despite a more complex pipeline, our design uses approximately 33% fewer slices while clocking 39% faster than a LEON3 based system built on a Xilinx Zynq X7CZ020.

关键词： Program processors field programmable gate arrays Pipelines Rockets Table lookup Fabrics

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Application-specific customisation of multi-threaded soft processors

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IEE PROCEEDINGS-COMPUTERS AND DIGITAL TECHNIQUES 2006年第3期153卷 173-180页

作者： Dimond, R. Mencer, O. Luk, W. Univ London Imperial Coll Sci Technol & Med Dept Comp London SW7 2RH England

A multi-threaded microprocessor with a customisable instruction set, CUStomisable threaded ARchitecture (CUSTARD), is proposed. CUSTARD features include design space exploration and a compiler for automatic selection of custom instructions. Custom instructions, optimised for a specific application, accelerate frequently performed computations by implementing them as dedicated hardware. field programmable gate array implementations of CUSTARD are evaluated using media and cryptography benchmarks, and commercial MicroBlaze processor is compared. As low as 28% area overhead for four interleaved threads and up to 355% speedup over a processor without custom instructions are demonstrated.

关键词： cryptography microprocessor chips FPGA implementation multi-threading Cryptography logic and switching circuits Microprocessor chips media benchmark MicroBlaze processor Data security Distributed systems software logic circuits design space exploration multithreaded microprocessor customisable instruction set dedicated hardware field programmable gate arrays instruction sets field programmable gate array custom instruction automatic selection cryptography benchmark interleaved thread customisable threaded architecture multithreaded soft processor Microprocessors and microcomputers

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A seamless DFT/FFT self-adaptive architecture for embedded radar applications 30

A seamless DFT/FFT self-adaptive architecture for embedded r...

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30th international conference on field-programmable logic and applications (FPL)

作者： Mazuet, Julien Narozny, Michel Dezan, Catherine Diguet, Jean-Philippe Thales LAS France Elancourt France UBO UBS Lab STICC CNRS Brest France

ISBN: (纸本)9781728199023

Radar is one of the domains where adaptability is paramount and algorithms must be adapted to system state. However, most systems include static implementations on FPGA or ASIC to process the massive amount of data from multiple sensors in parallel. the classic approach is to configure hardware logic through registers to switch radar modes, requiring to hardwire all configurations. In embedded systems, FPGA dynamic partial reconfiguration (DPR) is a promising solution to reuse scarce resources. In this paper, we use DPR for radar processing in order to switch between a classic discrete Fourier transform (DFT) sum and a fast Fourier transform (FFT) to enhance Doppler extraction. Our study explores the pros and cons of both methods. Based on these observations, we propose a new architecture and decision method that relies on Radar QoS for enabling an efficient self-adaptive solution. Finally, we provide a case study and a hardware-in-loop simulation with a reconfigurable radar implementation.

关键词： FPGA DPR radar QoS DFT

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ParaLaR: A Parallel FPGA router based on Lagrangian Relaxation 25

ParaLaR: A Parallel FPGA router based on Lagrangian Relaxati...

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25th international conference on field programmable logic and applications

作者： Hoo, Chin Hau Kumar, Akash Ha, Yajun Natl Univ Singapore Dept Elect & Comp Engn Singapore Singapore

ISBN: (纸本)9781467381239

Routing of nets is one of the most time consuming steps in the FPGA design flow. While existing works have described ways of accelerating the process through parallelization, they are not scalable. In this paper, we propose a scalable way of parallelizing the routing algorithm through Lagrangian relaxation. the FPGA routing problem is formulated as a linear programming problem, and the channel width constraints, which limit the amount of parallelism, are relaxed by incorporating them into the objective function. the result of the relaxation yields independent sub-problems that we solve using minimum Steiner tree algorithms. Our approach outperforms the state-of-the-art FPGA parallel router by producing an average self-relative speedup of 7.05X with 8 threads, reduces the total wire length by 22.4% on average and has similar channel width requirements as VPR, albeit at the cost of 7.5% longer critical path. Another advantage of our algorithm is that the number of threads and the order in which the nets are routed has totally no impact on the quality of result.

关键词： field programmable gate arrays (FPGA)

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Measure Twice and Cut Once: Robust Dynamic Voltage Scaling for FPGAs 26

Measure Twice and Cut Once: Robust Dynamic Voltage Scaling f...

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26th international conference on field-programmable logic and applications (FPL)

作者： Ahmed, Ibrahim Zhao, Shuze Trescases, Olivier Betz, Vaughn Univ Toronto Dept Elect & Comp Engn Toronto ON Canada

ISBN: (纸本)9782839918442

Although dynamic voltage scaling (DVS) is a popular power reduction solution that has been widely used by processors and ASICs, it is still not commercially adopted by FPGAs. A unique feature of FPGAs that leads to challenges in adopting DVS is that the critical path and hence the minimum safe V-dd depends on the configured application. We present a robust DVS technique that solves these challenges. For each application, we generate a calibration table (CT) that stores the actual failing points of that application on a specific FPGA, under various operating conditions. this CT is used to scale V-dd while the application is running to guarantee safe operation with minimal power consumption. We develop an automated tool (FRoC) that ensures a Fast-Robust-Calibration of the FPGA to any application using it. FRoC ensures that the calibration process is invisible to FPGA users and does not add any extra manual steps to the design process. We show that our proposed DVS technique achieves a 33% total power reduction on two large applications.

关键词： field programmable gate arrays (FPGA)

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A Technology Mapper for Depth-Constrained FPGA logic Cells 25

A Technology Mapper for Depth-Constrained FPGA Logic Cells

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25th international conference on field programmable logic and applications

作者： Jiang, Zhenghong Zgheib, Grace Lin, Colin Yu Novo, David Huang, Zhihong Yang, Liqun Yang, Haigang Ienne, Paolo Chinese Acad Sci Inst Elect Syst Programmable Chip Res Dept Beijing Peoples R China Ecole Polytech Fed Lausanne Sch Comp & Commun Sci CH-1015 Lausanne Switzerland

ISBN: (纸本)9781467381239

In the last decade, progress in logic synthesis has brought about new advantageous circuit representations. these representations, such as And-Inverter Graphs in the ubiquitous open-source synthesizer ABC, have inspired new designs of field programmable Gate Arrays (FPGAs), which, instead of using Look-Up Tables (LUTs), mimic the topology of the circuit representation in the basic logic cells. More recent examples are Majority-Inverter Graphs, another uniform representation which has triggered considerable interest in synthesis and which naturally suggests new logic cells. Yet, in this paper we observe how naively adapting technology mapping solutions for classic LUT-based FPGAs to these new architectures incurs severe shortcomings. the key issue is that LUTs are inherently input-constrained (the logic function they implement is irrelevant) and have generally a single output;on the other hand, logic cells made of uniform networks of some fundamental logic function (e.g., And-Invert) are constrained in terms of logic depth and multiple outputs are an integral feature. We introduce novel and effective solutions to address these differences;the result is a highly versatile mapper-thus enabling further research in these new architectures-with a significantly better performance than what is described in literature for one such architecture. Specifically, when we compare with the state of the art on one sample architecture, we obtain a significant decrease in area (on average 18% over several benchmarks) while also improving slightly the critical path (a reduction of 3%).

关键词： field programmable gate arrays (FPGA)

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A portable open-source controller for safe Dynamic Partial Reconfiguration on Xilinx FPGAs 25

A portable open-source controller for safe Dynamic Partial R...

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25th international conference on field programmable logic and applications

作者： Di Carlo, Stefano Prinetto, Paolo Trotta, Pascal Andersson, Jan Politecn Torino Dip Automat & Informat Turin Italy Cobham Gaisler AB Gothenburg Sweden

ISBN: (纸本)9781467381239

thanks to their flexibility, increasing performances and low Non-Recurrent Engineering costs, SRAM-based field programmable Gate Array (FPGA) devices often represent the preferred platforms for the final deployment of highly reliable systems. In this context, Dynamic Partial Reconfiguration (DPR) is far from being widely adopted due to the additional complexity introduced during the hardware design phase, and the dependability issues related to the FPGA reconfiguration process itself. this paper presents a portable open-source controller for safely enabling self dynamic and partial reconfiguration of systems implemented on Xilinx FPGAs. the controller embeds configurable error detection and correction circuitry that enables a safe DPR by monitoring for partial bitstreams data errors. Experiments highlight the high performances achieved and the limited hardware resources needed to implement it on different devices. the HDL source code has been made available through the popular open-source Cobham Gaisler GRLIB IP-cores library.(1)

关键词： hardware resource Reconfiguration field programmable gate arrays open source HIGH-PERFORMANCE Controllers error detection and correction dial pulse receiver

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