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检索条件"任意字段=17th International Conference on Field Programmable Logic and Applications"

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Data stream statistics over sliding windows: How to summarize 150 Million updates per second on a single node 29

Data stream statistics over sliding windows: How to summariz...

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29th international conference on field-programmable logic and applications (FPL)

作者： Chrysos, Grigorios Papapetrou, Odysseas Pnevmatikatos, Dionisios Dollas, Apostolos Garofalakis, Minos Tech Univ Crete Sch Elect & Comp Engn Iraklion Greece Eindhoven Univ Technol Dept Math & Comp Sci Eindhoven Netherlands ATHENA Res & Innovat Ctr Athens Greece

ISBN: (纸本)9781728148847

Traditional data management systems map information using centralized and static data structures. Modern applications need to process in real time datasets much larger than system memory. To achieve this, they use dynamic entities that are updated with streaming input data over a sliding window. For efficient and high performance processing, approximate sketch synopses of input streams have been proposed as effective means for the summarization of streaming data over large sliding windows with probabilistic accuracy guarantees. this work presents a system-level solution to accelerate the Exponential Count-Min (ECM) sketch algorithm on reconfigurable technology. Different reconfigurable architectures for the sketch structure that correspond to different cost and performance tradeoffs are presented. We map the proposed system-level ECM sketch architectures to a high-end modern HPC platform to achieve guaranteed and best-effort update rates up to 150 and 180 million tuples per second respectively. We compare the performance of the implemented system against the best optimized multi-thread software alternative and show that our scalable full-system accelerators outperform software solutions by 5-7.5x for Virtex6 devices and in excess of 10x for current Ultrascale devices.

关键词： Electronic countermeasures Microsoft Windows Complexity theory Histograms field programmable gate arrays IP networks throughput

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Designing Actively Secure, Highly Available Industrial Automation applications 17

Designing Actively Secure, Highly Available Industrial Autom...

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17th IEEE international conference on Industrial Informatics (INDIN)

作者： Tanveer, Awais Sinha, Roopak MacDonell, Stephen G. Leitao, Paulo Vyatkin, Valeriy Auckland Univ Technol IT & Software Engn Auckland New Zealand Inst Politecn Braganca Res Ctr Digitalisat & Intelligent Robot CeDRI Braganca Portugal Aalto Univ Helsinki Finland Lulea Univ Technol Lulea Sweden

ISBN: (纸本)9781728129273

programmable logic Controllers (PLCs) execute critical control software that drives Industrial Automation and Control Systems (IACS). PLCs can become easy targets for cyber-adversaries as they are resource-constrained and are usually built using legacy, less-capable security measures. Security attacks can significantly affect system availability, which is an essential requirement for IACS. We propose a method to make PLC applications more security-aware. Based on the well-known IEC 61499 function blocks standard for developing IACS software, our method allows designers to annotate critical parts of an application during design time. On deployment, these parts of the application are automatically secured using appropriate security mechanisms to detect and prevent attacks. We present a summary of availability attacks on distributed IACS applications that can be mitigated by our proposed method. Security mechanisms are achieved using IEC 61499 Service-Interface Function Blocks (SIFBs) embedding Intrusion Detection and Prevention System (IDPS), added to the application at compile time. this method is more amenable to providing active security protection from attacks on previously unknown (zero-day) vulnerabilities. We test our solution on an IEC 61499 application executing on Wago PFC200 PLCs. Experiments show that we can successfully log and prevent attacks at the application level as well as help the application to gracefully degrade into safe mode, subsequently improving availability.

关键词： Industrial automation and control systems programmable logic Controllers IEC 61499 active security protection Availability Intrusion detection and prevention

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Automatic Compiler Based FPGA Accelerator for CNN Training 29

Automatic Compiler Based FPGA Accelerator for CNN Training

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29th international conference on field-programmable logic and applications (FPL)

作者： Venkataramanaiah, Shreyas Kolala Ma, Yufei Yin, Shihui Nurvithadhi, Eriko Dasu, Aravind Cao, Yu Seo, Jae-sun Arizona State Univ Sch Elect Comp & Energy Engn Tempe AZ 85281 USA Intel Corp Intel Labs Hillsboro OR USA Intel Corp Programmable Solut Grp San Jose CA USA

ISBN: (纸本)9781728148847

Training of convolutional neural networks (CNNs) on embedded platforms to support on-device learning is earning vital importance in recent days. Designing flexible training hardware is much more challenging than inference hardware, due to design complexity and large computation/memory requirement. In this work, we present an automatic compiler based FPGA accelerator with 16-bit fixed-point precision for complete CNN training, including Forward Pass (FP), Backward Pass (BP) and Weight Update (WU). We implemented an optimized RTL library to perform training-specific tasks, and developed an RTL compiler to automatically generate FPGA-synthesizable RTL based on user-defined constraints. We present a new cyclic weight storage/access scheme for on-chip BRAM and off-chip DRAM to efficiently implement non-transpose and transpose operations during FP and BP phases, respectively. Representative CNNs for CIFAR-10 dataset are implemented and trained on Intel Stratix 10 GX FPGA using proposed hardware architecture, demonstrating up to 479 GOPS performance.

关键词： Convolution neural networks neural network training back-propagation hardware accelerator FPGA

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Software and Hardware Co-design for Low-Power HPC Platforms 1

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34th international conference on High Performance Computing (ISC High Performance)

作者： Ploumidis, Manolis Kallimanis, Nikolaos D. Asiminakis, Marios Chrysos, Nikos Xirouchakis, Pantelis Gianoudis, Michalis Tzanakis, Leandros Dimou, Nikolaos Psistakis, Antonis Peristerakis, Panagiotis Kalokairinos, Giorgos Papaefstathiou, Vassilis Katevenis, Manolis Fdn Res & Technol Hellas FORTH Iraklion Crete Greece

ISBN: (数字)9783030343569

ISBN: (纸本)9783030343569;9783030343552

In order to keep an HPC cluster viable in terms of economy, serious cost limitations on the hardware and software deployment should be considered, prompting researchers to reconsider the design of modern HPC platforms. In this paper we present a cross-layer communication architecture suitable for emerging HPC platforms based on heterogeneous multiprocessors. We propose simple hardware primitives that enable protected, reliable and virtualized, user-level communication that can easily be integrate in the same package with the processing unit. Using an efficient user-space software stack the proposed architecture provides efficient, low-latency communication mechanisms to HPC applications. Our implementation of the MPI standard that exploits the aforementioned capabilities delivers point-to-point and collective primitives with low overheads, including an eager protocol with end-to-end latency of 1.4 mu s. We port and evaluate our communication stack using real HPC applications in a cluster of 128 ARMv8 processors that are tightly coupled with FPGA logic. the network interface primitives occupy less than 25% of the FPGA logic and only 3 Mbits of SRAM while they can easily saturate the 16 Gb/s links in our platform.

关键词： field programmable gate arrays (FPGA)

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Self-Parameterized Chaotic Map: A Hardware-efficient Scheme Providing Wide Chaotic Range

Self-Parameterized Chaotic Map: A Hardware-efficient Scheme ...

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IEEE international conference on Electronics, Circuits and Systems (ICECS)

作者： Partha Sarathi Paul Anurag Dhungel Maisha Sadia Md Razuan Hossain Barry Muldrey Md Sakib Hasan University of Mississippi MS USA

We present a general method called “self-parameterization” for designing one-dimensional (1-D) chaotic maps that provide wider chaotic regions than existing 1-D maps. A wide chaotic range is a desirable property as it strengthens the security feature by enlarging the design space in many hardware-security applications, including reconfigurable logic and encryption. the proposed self-parameterized scheme reduces the hardware cost by involving only one chaotic map that modulates its own control parameter at every iteration by passing the map's previous output through a simple linear transformation. the widening of chaotic range after adding self-parameterization is demonstrated on three classical map functions: logistic, tent, and sine. Two hardware-efficient self-parameterized schemes are presented: one for field-programmable gate array (FPGA) implementation and the other one for integrated circuit (IC) implementation. the chaotic performance of the proposed scheme is evaluated with bifurcation plots and three established chaotic entropy metrics including, Lyapunov exponent, correlation coefficient, and correlation dimension.

关键词： Measurement Reconfigurable logic Bifurcation Hardware Entropy Encryption Security

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Information Metamaterials and Information Systems

Information Metamaterials and Information Systems

引用

international conference on Infrared and Millimeter Waves

作者： Tie Jun Cui Institute of Electromagnetic Space Southeast University Nanjing China State Key Laboratory of Millimeter Waves Southeast University Nanjing China

Metamaterials have great capabilities and flexibilities in controlling electromagnetic (EM) waves since their subwavelength meta-atoms can be designed and tailored in desired ways. However, once the structure-only metamaterials (i.e., passive metamaterials) are fabricated, their functions will be fixed. To control the EM waves dynamically, some active devices are integrated into the meta-atoms, yielding active metamaterials. Traditionally, the active metamaterials include tunable metamaterials and reconfigurable metamaterials, which have either small-range tunability or a few numbers of reconfigurability. Recently, a special kind of active metamaterials, digital coding and programmable metamaterials, have been presented, which can realize a large number of distinct functionalities and switch them in real time with the aid of field programmable gate array. More importantly, the digital coding representations of metamaterials make it possible to bridge the digital world and physical world using the metamaterial platform, and make the metamaterials process digital information directly, resulting in information metamaterials. In this regard, the information metamaterial is no longer an effective material or medium, but an information system. In this presentation, I will firstly introduce the evolution of metamaterials, and then present the concepts and basic principles of digital coding metamaterials and information metamaterials. With more details, I will introduce a series of information metamaterial systems, including the programmable meta-systems, software meta-systems, and intelligent meta-systems. Particularly, I will present two important applications of the information metamaterials: intelligent computational imaging and wireless communications.

关键词： Wireless communication Imaging Switches logic gates Metamaterials Encoding Software

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Towards an Efficient Accelerator for DNN-based Remote Sensing Image Segmentation on FPGAs 29

Towards an Efficient Accelerator for DNN-based Remote Sensin...

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29th international conference on field-programmable logic and applications (FPL)

作者： Liu, Shuanglong Luk, Wayne Imperial Coll London Dept Comp London England

ISBN: (纸本)9781728148847

Among popular techniques in remote sensing image (RSI) segmentation, Deep Neural Networks (DNNs) have gained increasing interest but often require high computation complexity, which largely limits their applicability in on-board space platforms. therefore, various dedicated hardware designs on FPGAs have been developed to accelerate DNNs. However, it imposes difficulty on the design of efficient accelerators for DNN-based segmentation algorithms, since they need to perform both convolution and deconvolution which are two fundamentally different types of operations. this paper proposes a uniform architecture to efficiently implement both convolution and deconvolution in one vector multiplication module. this architecture is further optimized through exploiting different levels of parallelism and layer fusion to achieve low latency for RSI segmentation tasks. Moreover, an optimized DNN model is developed for real-time RSI segmentation, which shows preferable accuracy compared to other methods. the proposed hardware accelerator efficiently implements the DNN model on Intel's Arria 10 device, demonstrating 1578 GOPS of throughput and 17.4 ms of latency, i.e., 57 images per second.

关键词： Computer architecture Image segmentation Convolution Deconvolution Kernel field programmable gate arrays Computational modeling

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Timing-aware routing in the RapidWright framework 29

Timing-aware routing in the RapidWright framework

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29th international conference on field-programmable logic and applications (FPL)

作者： Liu, Leo Kapre, Nachiket Univ Waterloo Sch Elect & Comp Engn Waterloo ON Canada

ISBN: (纸本)9781728148847

We can extract approximate, fine-grained timing information of routing resources of Xilinx FPGAs using the RapidWright open-source framework. the absence of timing information makes it difficult to implement timing-aware FPGA CAD tools using RapidWright. It is impractical to invoke Vivado's timing analysis engine for each choice within an optimization loop of your custom CAD algorithm as that would slow down execution by orders of magnitude. We route a set of one-time calibration tests on the FPGA using Vivado to extract path delays, and setup a system of linear equations based on the unknown delays associated with each routing resource used in the calibration route. We run this calibration for an interconnect tile but generalize the result to the entire FPGA due to device symmetry. We then solve these equations using least squares approximation as the resulting system is low-rank. this is due to the routing restrictions imposed by the FPGA fabric for legality of the connection and correctness of Vivado's timing analysis. We are able to learn an approximate timing model for RapidWright that is within 1% error (0.01 ns) of Vivado timing analysis by running approximate to 30 calibration runs and needing under 60 seconds of Vivado timing analysis. We demonstrate this technique on Xilinx XCKU115 FPGA (-3, -2, and -1 speed grades). the open-source RapidRoute custom router previously lost to Vivado by as much as 0.3-0.4 ns on timing slack when using a crude timing model. With our timing model enhancements, we allow RapidRoute to close the slack gap with Vivado and even outperform Vivado marginally on occasion. Our timing model generation is lightweight and can be discovered for each FPGA device instead of bundling memory-hungry timing libraries with RapidWright.

关键词： field programmable gate arrays Routing Delays Tools Mathematical model Calibration

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Real-Time Multi-Pedestrian Detection in Surveillance Camera using FPGA 29

Real-Time Multi-Pedestrian Detection in Surveillance Camera ...

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29th international conference on field-programmable logic and applications (FPL)

作者： Jinguji, Akira Sada, Youki Nakahara, Hiroki Tokyo Inst Technol Tokyo Japan

ISBN: (纸本)9781728148847

In surveillance cameras, pedestrians and objects are detected using Convolutional Neural Network (CNN) based Object Detection such as YOLO and SSD. Since the size of the CNN input image is fixed, small objects cannot be detected when the high-resolution image is resized. By splitting image and applying object detection to each split image, CNN can detect small objects and take advantage of the high performance of the FPGA. We demonstrate an object detector by splitting the given image as stream data to YOLOv2 on an FPGA which has a very high performance. It achieved both practical speed and accuracy. Due to the difference in scale between training data and test data, the detection of small objects fails when the granularity of split is small. Splitting the image matches the scale of the data. When detection throughput is high enough, it detects many objects with a practical speed. We demonstrate the comparison of FPGA and mobile GPU in the proposed image split method of object detection. We implement Object Detection Systems by Xilinx ZCU104 FPGA board and NVIDIA Mobile GPU boards with a USB camera. the image split method can be adapted as it is to all implementations of object detection. We compare the performance of the FPGA and GPU. As a result of the experiment, FPGA achieves 547.0 FPS per image and is 3.9 times faster than Mobile GPU. When the given image is split into 4 x 4 grids, the system realizes 34.2 FPS and it satisfies the real-time requirement on the standard camera(30FPS). We showed that ultra-fast object detection can be used to improve accuracy.

关键词： field programmable gate arrays Object detection Task analysis Graphics processing units throughput Pipeline processing Cameras

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FPGA-based Training Accelerator Utilizing Sparseness of Convolutional Neural Network 29

FPGA-based Training Accelerator Utilizing Sparseness of Conv...

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29th international conference on field-programmable logic and applications (FPL)

作者： Nakahara, Hiroki Sada, Youki Shimoda, Masayuki Sayama, Kouki Jinguji, Akira Sato, Shimpei Tokyo Inst Technol Tokyo Japan

ISBN: (纸本)9781728148847

Training of convolutional neural networks (CNNs) is almost exclusively performed on large clusters of GPUs. However, it consumes vast amounts of power. thus, high-speed training systems superior in low-power consumption are desired. this paper proposes an 'VGA-based training accelerator utilizing a sparseness of a CNN, which consists of universal convolutional units and pooling units with distributed stacks. the proposed universal convolution architecture supports various convolution operations, such as the point-wise, depth-wise, large kernel and atrous convolutions used in the modern CNN. Additionally, we utilize a fine-tuning scheme, which loads a pre-trained dense CNN to reduce the memory size for the training process, while it considers important connectivity to preserve recognition accuracy. Our training scheme reduces 85% parameters to accelerate the training computation and reduce on-chip size. thus, it eliminates energy-consuming DRAM accesses. We implemented the proposed training accelerator on a Xilinx Virtex UltraScale+ VC1525 acceleration development board. Experimental results show that the proposed sparse CNN training accelerator on the FPGA can achieve four times faster, 2.9 times lower power consumption, and 11.6 limes better performance per power, compared to the existing NVIDIA RTX2081111 GPO.

关键词： Training Convolution Two dimensional displays field programmable gate arrays Kernel System-on-chip Convolutional neural networks

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