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FPGA-based Training Accelerator Utilizing Sparseness of Convolutional Neural Network 29

FPGA-based Training Accelerator Utilizing Sparseness of Conv...

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29th international conference on field-programmable logic and applications (FPL)

作者： Nakahara, Hiroki Sada, Youki Shimoda, Masayuki Sayama, Kouki Jinguji, Akira Sato, Shimpei Tokyo Inst Technol Tokyo Japan

ISBN: (纸本)9781728148847

Training of convolutional neural networks (CNNs) is almost exclusively performed on large clusters of GPUs. However, it consumes vast amounts of power. thus, high-speed training systems superior in low-power consumption are desired. this paper proposes an 'VGA-based training accelerator utilizing a sparseness of a CNN, which consists of universal convolutional units and pooling units with distributed stacks. the proposed universal convolution architecture supports various convolution operations, such as the point-wise, depth-wise, large kernel and atrous convolutions used in the modern CNN. Additionally, we utilize a fine-tuning scheme, which loads a pre-trained dense CNN to reduce the memory size for the training process, while it considers important connectivity to preserve recognition accuracy. Our training scheme reduces 85% parameters to accelerate the training computation and reduce on-chip size. thus, it eliminates energy-consuming DRAM accesses. We implemented the proposed training accelerator on a Xilinx Virtex UltraScale+ VC1525 acceleration development board. Experimental results show that the proposed sparse CNN training accelerator on the FPGA can achieve four times faster, 2.9 times lower power consumption, and 11.6 limes better performance per power, compared to the existing NVIDIA RTX2081111 GPO.

关键词： Training Convolution Two dimensional displays field programmable gate arrays Kernel System-on-chip Convolutional neural networks

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FPGA-based Simulated Bifurcation Machine 29

FPGA-based Simulated Bifurcation Machine

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29th international conference on field-programmable logic and applications (FPL)

作者： Tatsumura, Kosuke Dixon, Alexander R. Goto, Hayato Toshiba Co Ltd Corp Res & Dev Ctr Tokyo Japan

ISBN: (纸本)9781728148847

Since many combinatorial optimization problems can be mapped onto ground-state search problems of Ising models, special-purpose machines for Ising problems have attracted intense attention. Simulated bifurcation (SB) is a recently proposed algorithm to solve these Ising problems. One of the remarkable features of SB is the high-degree parallelism underlying in the algorithm, providing an opportunity to solve the Ising problems very fast by massively parallel processing. In this work, we implement the SB algorithm on FPGAs by designing massively parallel custom circuits. We then compare the FPGA-based SB machines with a state-of-the-art machine called a coherent Ising machine (CIM), a highly optimized implementation of simulated annealing (SA), and GPU-based SB machines. SB machines with spin size of 2,048/4,096 (2K/4K) on an Arria10 GX1150 FPGA have 8,192 processing elements for the matrix-vector multiplication (MM) modules (the most computationally intensive part) and achieve computation throughput of 1,873/2,027 GMAC/s for the MM modules, outperforming 2K/4K SB machines on an Nvidia Tesla V100 GPU (113/183 GMAC/s). the 2K FPGA-SB solves all-to-all connected 2000-node MAX-CUT problem 14X (/124X) faster than the CIM (/the highly-optimized SA), with much better energy efficiency (288X better than the CIM).

关键词： Oscillators Bifurcation Parallel processing field programmable gate arrays Optimization Graphics processing units Computational complexity

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An FPGA Implementation of Real-time Object Detection with a thermal Camera 29

An FPGA Implementation of Real-time Object Detection with a ...

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29th international conference on field-programmable logic and applications (FPL)

作者： Shimoda, Masayuki Sada, Youki Kuramochi, Ryosuke Nakahara, Hiroki Tokyo Inst Technol Tokyo Japan

ISBN: (纸本)9781728148847

We demonstrate a sparse YOLOv2-based object detector with a thermal camera. A thermal camera outputs pixel values which represent heat (temperature), and the output is gray-scale images. Since the thermal cameras do not depend on whether there is the light or not unlike other visible range cameras, object detection using the thermal camera is reliable without ambient surrounding. this topic is of a broad interest in object surveillance[1] and action recognition[2]. However, since it is challenging to extract informative features from the thermal images, the implementation challenges of the object detector with high accuracy remain. In recent works, convolutional neural networks (CNNs) outperform conventional techniques, and a variety of object detectors based on the CNNs have been proposed. the representative networks are single-shot detectors that consist of a CNN and infer locations and classes simultaneously (e.g., SSD[3] and YOLOv2[4]). Although the primary advantage of the type is that it enables to train detection and classification simultaneously, the resulting increased computation time and area requirements can cause problems of implementation on an FPGA. Also, as for the proposed networks on RGB three channel images, one of the problems is false positive;the realization of more reliable object detector is required. To realize a real-time reliable object detector, we investigate an FPGA implementation of a sparse YOLOv2-based one whose inputs are four-channel images that consist of both the RGB and the thermal ones. In this demonstration, we show a performance comparison between an RGB-based detector and our proposed one on FPGAs.

关键词： Detectors field programmable gate arrays Cameras Object detection conferences Reliability Feature extraction

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Power Management in FPGAs using a Temperature Aware Place and Route Methodology 9

Power Management in FPGAs using a Temperature Aware Place an...

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9th IEEE international conference on Communication and Signal Processing, ICCSP 2020

作者： Gopikrishna, P.V. Kulkarni, G.H. KLS Gogte Institute of Technology Department of Electronics and Communication Engineering Belagavi India Jain College of Engineering Department of Electrical and Electronics Engineering Belagavi India

ISBN: (纸本)9781728149882

Due to increase in demand for low power electronic systems in recent years, significant research and development work is happening in the low power domain. this is especially true for field programmable Gate Arrays (FPGAs), which dissipate significantly more power than fixed-logic implementations. Power is a critical issue when FPGA applications are considered. In spite of the significant improvements in the recent past, power dissipation in FPGAs is significant. With the scaling down of CMOS process technology, factors like higher total interconnect capacitance per chip, higher operating frequencies, and increase in leakage will continue to increase the power density. All these factors will increase the operating temperature of the device which leads to the production of heat inside the chip. the final implementation is affected by the problems associated with the increase in heat produced. Some critical issues associated with temperature rise are the system reliability, the packaging of the chip and the life cycle of the final product. the dominance of the heat problem is one of the key design issues, which needs to be addressed. It is observed that in FPGAs the central portion of the device gets heated up due to the concentration of active Configurable logic Blocks (CLBs) at the centre. Effect of arranging the unused CLBs at different places across the FPGA and the thermal distribution is examined in the present work. this paper aims at minimizing the total power consumption and also to redistribute it across the entire FPGA. A temperature-aware placement and routing is considered, by placing the unused CLBs across different locations of the FPGA so as to obtain uniform temperature profile across the entire cross section of FPGA. Since temperature is dependent on the switching activity of the hardware resources of FPGA, the proposed methodology aims at redistributing the switching activity over the FPGA resources. © 2020 IEEE.

关键词： field programmable gate arrays (FPGA)

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Real-time Performance Evaluation of Single Phase 7 Level Z-Source Boost Inverter

Real-time Performance Evaluation of Single Phase 7 Level Z-S...

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international conference on Electrical Energy Systems (ICEES)

作者： Hanuman Prasad Kishor V. Bhadane Parveen Kumar Model Institute of Engineering and Technology Jammu India Amrutvahini College of Engineering Sangamner Maharashtra India

ISBN: (数字)9781728176123

ISBN: (纸本)9781728176130

Multilevel inverter has been familiarized as a popular topology for DC-AC power conversion. this paper illustrates the real-time performance evolution of seven level zsource diode clamp multilevel inverter. the field programmable gate array (FPGA) integrated real time simulators consists of multiprocessor and computer clusters are the main hardware platforms for real-time simulations. the real time (RI) lab software enables the parallel simulation of an electrical circuit on clusters of personal computer running at sampling time 10 μs. the integration of multilevel inverter and z-source energy conversion are used for DC-AC converter for high power applications with low total harmonics distortion. An impedance network has two passive elements such as two inductors and two capacitors connected between DC power source and multilevel inverter circuit. It provides a unique feature such as the boost the inverter output voltage and reduces the harmonic content in the output voltage as compared to the classic multilevel inverter. the real time results are verified the proposed system with a specified time step 10 μs and frequency is 10 KHz.

关键词： Computational modeling logic gates Multilevel inverters DC-AC power converters Real-time systems Integrated circuit modeling field programmable gate arrays

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field programmable gate array hardware accelerator of prime implicants generation for single-output boolean functions minimization 17

Field programmable gate array hardware accelerator of prime ...

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17th IEEE international conference on Emerging eLearning Technologies and applications, ICETA 2019

作者： Mados, B. Bilanova, Z. Chovancova, E. Adam, N. Technical University of Košice Department of Computers and Informatics Faculty of Electrical Engineering and Informatics Košice04200 Slovakia

ISBN: (纸本)9781728149677

the paper deals with the problematics of two-level single-output Boolean functions minimization which is important for many fields of science and technology including logic and control systems design, software engineering, artificial intelligence and others. In this work proposed solution, which is aimed to the production of prime implicants for particular Boolean functions, as the first step of Boolean functions minimization, is based on the use of designed hardware accelerator using field programmable Gate Array (FPGA) technology. As the part of this work, input and output binary vectors encoding is proposed along with the combinational logic module, described using VHDL. Module is implemented into Xilinx Kintex-7 FPGA KC705 Evaluation Kit evaluation board. Advantage of proposed hardware accelerator is in extremely small time complexity in comparison to the algorithms which are utilizing classical CPU based solutions. Another advantage is in constant time of prime implicants generation in case of the same number of input variables of Boolean function regardless of ON set cardinality. Disadvantage of the solution is that it is not possible to define don't care set and in space complexity which is rising quickly according to the number of input variables of Boolean function. © 2019 IEEE.

关键词： Boolean functions

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Power Optimization of KNN Algorithm Based on FPGA

Power Optimization of KNN Algorithm Based on FPGA

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international conference on Engineering Technology and their applications (IICETA)

作者： Fadi T. Naser Sarah N. Hadi Ivan A. Hashim University of Technology Baghdad Iraq Al-Salam University College Baghdad Iraq

ISBN: (纸本)9781665494625

In modern field programmable Gate Array (FPGA) digital systems, power dissipation has become a critical concern to design digital systems. As size shrinks and density increases in chips, it will be a challenge to design high-performance and low-power digital systems. therefore, it is important to reduce the power dissipation in these systems by using power-optimization techniques. Most digital systems have different mathematical operations and machine learning algorithms in their architectures. this paper focuses on K-Nearest Neighbor (KNN) algorithm. A KNN algorithm takes more extended time, larger area and consumes more power than other basic computational algorithms. thus, recent digital systems require high speed and low-power KNN algorithm in order to improve its performance. In this work, dynamic-power consumption is targeted. Different designs of KNN algorithms, such as KNN design Based on Hard FPGA Blocks, Hybrid KNN Design, and KNN Algorithm Based on the VHDL Approach are suggested. A new power-optimization technique is suggested. the new VHDL technique shows the highest dynamic power saving, about (90%) than the other proposed designs.

关键词： VHDL Machine learning algorithms Digital systems Heuristic algorithms Switches logic gates Power dissipation

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Accelerating Bayesian Inference on Structured Graphs Using Parallel Gibbs Sampling 29

Accelerating Bayesian Inference on Structured Graphs Using P...

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29th international conference on field-programmable logic and applications (FPL)

作者： Ko, Glenn G. Chai, Yuji Rutenbar, Rob A. Brooks, David Wei, Gu-Yeon Harvard Univ Cambridge MA 02138 USA Univ Pittsburgh Pittsburgh PA USA

ISBN: (纸本)9781728148847

Bayesian models and inference is a class of machine learning that is useful for solving problems where the amount of data is scarce and prior knowledge about the application allows you to draw better conclusions. However, Bayesian models often requires computing high-dimensional integrals and finding the posterior distribution can be intractable. One of the most commonly used approximate methods for Bayesian inference is Gibbs sampling, which is a Markov chain Monte Carlo (MCMC) technique to estimate target stationary distribution. the idea in Gibbs sampling is to generate posterior samples by iterating through each of the variables to sample from its conditional given all the other variables fixed. While Gibbs sampling is a popular method for probabilistic graphical models such as Markov Random field (MRF), the plain algorithm is slow as it goes through each of the variables sequentially. In this work, we describe a binary label MRF Gibbs sampling inference architecture and extend it to 64-label version capable of running multiple perceptual applications, such as sound source separation and stereo matching. the described accelerator employs a chromatic scheduling of variables to parallelize all the conditionally independent variables to 257 samplers, implemented on the FPGA portion of a CPU-FPGA SoC. For real-time streaming sound source separation task, we show the hybrid CPU-FPGA implementation is 230x faster than a commercial mobile processor, while maintaining a recommended latency under 50 ms. the 64-label version showed 137x and 679x speedups for binary label MRF Gibbs sampling inference and 64 labels, respectively.

关键词： bayesian inference markov chain monte carlo gibbs sampling hardware accelerator markov random field

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A Simple Heterogeneous Redundant Design Method for Finite State Machines on FPGAs 13th

A Simple Heterogeneous Redundant Design Method for Finite St...

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13th international conference on Complex, Intelligent, and Software Intensive Systems (CISIS)

作者： Itagawa, Takanori Kamasaka, Ryo Shibata, Yuichiro Nagasaki Univ 1-14 Bunkyo Machi Nagasaki 8528521 Japan

ISBN: (纸本)9783030223540;9783030223533

For FPGA applications in the application domains requiring a high degree of functional safety such as automotive and industrial infrastructure, simple homogeneous redundant logic design, where the same hardware modules are simply replicated, is not enough. In order to improve tolerance to common cause fault, heterogeneous redundant design, where different implementation approaches are taken for realizing the same logic functionality, is crucial. However, manual redundant design tends to place a burden on designers, reducing productivity of system development. To cope with this problem, this paper proposes a systematic heterogeneous redundant design approach for finite state machines on FPGAs, focusing on the diversity of state encoding methods. With this approach, designers can easily combine the state machines with different encoding to form heterogeneous redundancy, by inserting simple directives into RTL source code. In order to evaluate the effectiveness of the proposed approach, timing analysis of post-layout netlists is performed under an overclock situation as an example of common cause fault. the evaluation results demonstrate the proposed approach improves the error detection rate compared to conventional homogeneous redundant designs. It is also discussed how the choice of state encoding methods impacts the error detection rate.

关键词： field programmable gate arrays (FPGA)

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4th international Workshop on FPGAs for Software Programmers, FSP 2017, co-located with international conference on field programmable logic and applications, FPL 2017

4th International Workshop on FPGAs for Software Programmers...

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international Workshop on FPGAs for Software Programmers, FSP 2017, co-located with international conference on field programmable logic and applications, FPL 2017

ISBN: (纸本)9783800744435

the proceedings contain 10 papers. the topics discussed include: a case for better integration of host and target compilation when using OpenCL for FPGAs;PCIeHLS: an OpenCL HLS framework;SOCAO: source-to-source OpenCL compiler for Intel-Altera FPGAs;a highly efficient and comprehensive image processing library for C++-based high-level synthesis;accelerating Linux bash commands on FPGAs using partial reconfiguration;acceleration of solving quadratic assignment problems on programmable SoC using High level synthesis;spatial memory trace prediction;on the HLS design of bit-level operations and custom data types;and using GCC analysis techniques to enable parallel memory accesses in HLS.

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