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检索条件"任意字段=17th International Conference on Field Programmable Logic and Applications"

共 1932 条记录，以下是21-30 订阅

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Proceedings - 2009 FPL 09: 19th international conference on field programmable logic and applications, FPL 2009: Preface

FPL 09: 19th International Conference on Field Programmable ...

引用

FPL 09: 19th international conference on field programmable logic and applications 2009年 iii-iv页

作者： Daněk, Martin Nelson, Brent

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Harnessing programmable logic for Quaternion Multiplication 20th

Harnessing Programmable Logic for Quaternion Multiplication

引用

20th EAI international conference on Computer Science and Education in Computer Science, CSECS 2024

作者： Gorbounov, Yassen Chen, Hao New Bulgarian University Sofia Bulgaria China University of Mining and Technology Xuzhou221000 China

ISBN: (纸本)9783031843112

Quaternions are four-dimensional hyper-complex numbers discovered by Sir William Hamilton in the 19th century. Compared to Euler angles, quaternions allow combining rotations in three-dimensional space and help overcome the problem of not being able to rotate about an axis regardless of rotation about other axes. they find numerous applications in various fields such as mechatronics, computer graphics and signal processing. However, the computational complexity of quaternion multiplication limits its effectiveness in real-time applications. To solve this problem, the paper proposes a hardware-oriented solution based on a programmable logic device (PLD). the design structure is based on the parallel processing and reconfiguration capabilities of the PLD, which can significantly improve the quaternion multiplication performance compared to traditional implementations based on a purely software approach. the paper covers the elaborated multiplier architecture and discusses its advantages in terms of performance and resources used. the experimental work performed highlights the flexibility of the approach used and demonstrates its effectiveness in accelerating quaternion multiplication, making it suitable for real-time applications. © ICST Institute for Computer Sciences, Social Informatics and Telecommunications Engineering 2025.

关键词： Computer circuits

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Proceedings - 2010 international conference on field programmable logic and applications, FPL 2010: Message from the conference chairs

Proceedings - 2010 International Conference on Field Program...

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Proceedings - 2010 international conference on field programmable logic and applications, FPL 2010 2010年 xv页

作者： Ferrandi, Fabrizio Santambrogio, Marco D. Nurmi, Jari Politecnico di Milano Italy Tampere University of Technology Finland

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Proceedings - 2010 international conference on field programmable logic and applications, FPL 2010: Message from the steering committee

Proceedings - 2010 International Conference on Field Program...

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Proceedings - 2010 international conference on field programmable logic and applications, FPL 2010 2010年 xvi页

作者： Lysaght, Patrick Luk, Wayne Cheung, Peter Y.K. Xilinx Inc. United States Imperial College London United Kingdom

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Power Based Side-Channel Analysis for Lightweight Cipher Ltlbc

Power Based Side-Channel Analysis for Lightweight Cipher Ltl...

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international conference on Computer and Automation Engineering, ICCAE

作者： Yusuke Nozaki Shu Takemoto Masaya Yoshikawa Dept. Information Engineering Meijo University Nagoya Japan

ISBN: (数字)9798331533816

ISBN: (纸本)9798331533823

Industry 5.0 requires security measures because of the threat of cyber attacks and data leaks from outside due to the communication of a variety of data. As a cryptographic technique for security measures, LTLBC, a low-latency lightweight cipher that can be used in industrial equipment at high speed, is attracting attention. On the other hand, the security of cryptographic circuits requires the tamper resistance against sidechannel analysis. So far, tamper resistance evaluation of LTLBC is insufficient. therefore, this study proposes an evaluation method to verify the security of LTLBC against side-channel analysis. Experiments using a field programmable gate array show that the proposed method can be used to evaluate the tamper resistance of LTLBC against side-channel analysis using 1,400 waveforms.

关键词： Resistance Hands Ciphers Power demand Hardware security Circuits logic gates Low latency communication Fifth Industrial Revolution field programmable gate arrays

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Secure Medical Image Transmission Using the RLCD Algorithm

Secure Medical Image Transmission Using the RLCD Algorithm

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Sentiment Analysis and Deep Learning (ICSADL), international conference on

作者： C Sheeba Joice S Hitha Shanthini K Harsha S Gopika Department of Electronics and Communication Engineering Saveetha Engineering College Chennai India

ISBN: (数字)9798331523923

ISBN: (纸本)9798331523930

As digital platforms increasingly manage sensitive medical information, securing the transmission of medical images is essential to maintain confidentiality and data integrity. this project introduces an efficient and secure cryptographic framework specifically designed for medical image encryption using Reversible logic Cryptography Design (RLCD). the approach incorporates Linear Feedback Shift Registers (LFSR) combined with XOR gates, enabling low-power and high-speed encryption and decryption to protect patient data without sacrificing performance. By integrating reversible logic gates, this system effectively reduces energy dissipation and prevents information loss, making it well-suited for applications where data accuracy is critical. Implemented in Verilog HDL and deployed on a field programmable Gate Array (FPGA), this design provides a robust solution to address the unique security demands in medical imaging.

关键词： Sentiment analysis programmable logic arrays logic gates Hardware Software Encryption Hardware design languages field programmable gate arrays Biomedical imaging Python

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Meta-Heuristic Optimization of Custom Heterogeneous Blocks Defined eFPGA Design

Meta-Heuristic Optimization of Custom Heterogeneous Blocks D...

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international conference on VLSI Design

作者： D V Bhargav G Pradyumna Madhav Rao IIIT Bangalore

ISBN: (数字)9798331522445

ISBN: (纸本)9798331522452

Modern field-programmable Gate Arrays (FPGAs) are highly versatile, with reconfigurable logic functionality that allows designers to create custom designs. Unlike traditional fixed-function integrated circuits, FPGAs are reconfigured multiple times to perform different tasks, making them ideal for various applications. An Embedded FPGA (eFPGA) takes the concept of an FPGA and integrates it as an IP core within a larger System-on-Chip (SoC) or Application-Specific Integrated Circuit (ASIC). the proposed work employs Non-dominated Sorting Genetic Algorithm-II (NSGA-II) to evolve efficient and high-performing eFPGA architectures with reduced critical path delay and power defined by a sufficient number of Configurable logic Blocks (CLBs), custom Digital Signal Processors (DSPs) and Block RAM (BRAMs) for targetting workload under consideration. As a result, this work presents a well-balanced eFPGA architecture layout obtained for four workloads equipped with different numbers of heterogeneous and configurable logic blocks. the results showed a significant improvement of 44.62% in hardware parameters.

关键词： Layout Metaheuristics Digital signal processors Signal processing algorithms Computer architecture Silicon Fabrics logic IP networks field programmable gate arrays

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Obstacle Avoidance: Transfer Learning and FPGA for Acceleration

Obstacle Avoidance: Transfer Learning and FPGA for Accelerat...

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Mobile Computing and Sustainable Informatics (ICMCSI), international conference on

作者： Jeyalakshmi. V Arjun Chakkrapani Preethaa Jansirani Kripa. S Vaithiyanathan. D Department of Electronics and Communication Engineering College of Engineering Guindy Chennai Tamil Nadu India Department of Electronics and Communication Engineering NIT Delhi India

ISBN: (数字)9798331522667

ISBN: (纸本)9798331522674

Obstacle detection and avoidance have historically been manual processes. With the advent of neural networks, many processing tasks have been made autonomous with more efficient by obtaining a wide variety of data from their surroundings to perform the next move. Training these networks is computationally intensive, which became the driving force behind transfer learning. field programmable Gate Arrays (FPGAs) which revolutionized reconfigurable logic is the next choice considered the opportunity to interleave the processing tasks between a general-purpose processor and dedicated logic blocks. Extending this concept to collision detection and using hardware acceleration to speed up the decision process can be highly beneficial, especially in such time critical applications. In this article, the idea above has been reviewed, and a method to implement the system has been proposed.

关键词： Training Neural networks Transfer learning Speech recognition Reconfigurable logic logic gates throughput Collision avoidance field programmable gate arrays Python

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Demo: An RFSoC-Based Testbed for Over-the-Air Wireless Transceiver at Millimeter Wave Frequency

Demo: An RFSoC-Based Testbed for Over-the-Air Wireless Trans...

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international Communication Systems and Networks and Workshops, COMSNETS

作者： Jeet Tekchandani Jai Mangal Sumit J. Darak Shobha Sundar Ram Electronics & Communication Department Indraprastha Institute of Information Technology Delhi India

ISBN: (数字)9798331531195

ISBN: (纸本)9798331531201

the millimeter wave (mmW) frequency spectrum has been explored recently for large bandwidth communication. At these frequencies, narrow directional beams are required for communication since the signal attenuation is high due to atmospheric absorption. this work presents an AMD RFSoC and Sivers Semiconductors analog front-end based hardware testbed capable of directional communication via analog beamforming at mmW. the proposed testbed comprises orthogonal frequency division multiplexing (OFDM) based baseband physical layer and digital front-end on an ARM processor and field programmable gate array (FPGA), respectively, integrated with high-speed data converters of the RFSoC. the RFSoC output at sub-6GHz is integrated with a mmW multi-antenna analog-front end for over-the-air communication at 29.8 GHz. We demonstrate end-to-end communication over the air and present bit error rate (BER) analysis in the presence of radio frequency impairments and beam misalignments in real radio channels.

关键词： OFDM Wireless networks Bit error rate logic gates Physical layer Hardware Transceivers Frequency division multiplexing Millimeter wave communication field programmable gate arrays

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NanoSoftController: A Minimal Soft Processor for System State Control in FPGA Systems 24th

NanoSoftController: A Minimal Soft Processor for System Stat...

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24th international conference on Embedded Computer Systems: Architectures, Modeling, and Simulation

作者： Weissbrich, Moritz Seidlitz, Germain Paya-Vaya, Guillermo Tech Univ Carolo Wilhelmina Braunschweig Chair Chip Design Embedded Comp Muhlenpfordtstr 22-23 D-38106 Braunschweig Germany

ISBN: (纸本)9783031783760;9783031783777

In many FPGA-based systems, only sequential system control structures modeled by finite state machines are actually required. In order to deal with complexity, design time, and verification issues, which are weaknesses of traditional hardware description languages, it may be preferred to describe the control flow behaviorally in software. However, it is reported that high-level synthesis for FPGA often generates inferior results in terms of resources and performance when translating software-style control flow description to hardware. In this paper, the NanoSoftController is proposed as an open-source soft processor, which is optimized for minimal and efficient logic resource usage on FPGA platforms. It is targeted at processing sequential finite state machine functionality in software, featuring a compact ISA for control flow in embedded systems and a tiny accumulator-based data path. Furthermore, an efficient mapping of memory to small distributed LUT RAM instances enables its use as a system state machine controller in even very resource-constrained FPGA designs, requiring only 104 slice LUTs and 76 slice registers in total. However, despite all optimizations, in a case study with high-level synthesis results of three reference software-style control applications, i.e., electronic door lock, smart glucose sensor, and sequential sensor network node, a better resource efficiency could not be shown. We evaluate the negative results and provide lessons we learned from them.

关键词： Accumulator architecture FPGA High-level synthesis Microcontroller programmable state machine Soft processor

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