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FP-Stereo: Hardware-Efficient Stereo Vision for Embedded applications

FP-Stereo: Hardware-Efficient Stereo Vision for Embedded App...

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international conference on field programmable logic and applications

作者： Jieru Zhao Tingyuan Liang Liang Feng Wenchao Ding Sharad Sinha Wei Zhang Shaojie Shen Hong Kong University of Science and Technology Alibaba Group India Institute of Technology Goa

ISBN: (数字)9781728199023

ISBN: (纸本)9781728199030

Fast and accurate depth estimation, or stereo matching, is essential in embedded stereo vision systems, requiring substantial design effort to achieve an appropriate balance among accuracy, speed and hardware cost. To reduce the design effort and achieve the right balance, we propose FP-Stereo for building high-performance stereo matching pipelines on FPGAs automatically. FP-Stereo consists of an open-source hardware-efficient library, allowing designers to obtain the desired implementation instantly. Diverse methods are supported in our library for each stage of the stereo matching pipeline and a series of techniques are developed to exploit the parallelism and reduce the resource overhead. To improve the usability, FP-Stereo can generate synthesizable C code of the FPGA accelerator with our optimized HLS templates automatically. To guide users for the right design choice meeting specific application requirements, detailed comparisons are performed on various configurations of our library to investigate the accuracy/speed/cost trade-off. Experimental results also show that FP-Stereo outperforms the state-of-the-art FPGA design from all aspects, including 6.08% lower error, 2x faster speed, 30% less resource usage and 40% less energy consumption. Compared to GPU designs, FP-Stereo achieves the same accuracy at a competitive speed while consuming much less energy.

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Research and implementation of an automatic simulation tool

Research and implementation of an automatic simulation tool

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international conference on Dependable Systems and their applications (DSA)

作者： Liu Tang You Li Hongwei Wang Huan Zhao Luze Ma Yuming Sun Beijing Sunwise Information Technology Ltd. China

ISBN: (数字)9780738124223

ISBN: (纸本)9781665419536

With the rapidly increasing of space missions, FPGA is more widely used for its ability of single chip approaching 10 million gates of logic and 10 million bits of memory. More and more challenges are posed to FPGA design and verification, with the characteristics of a tight schedule, a burdensome task, momentous responsibilities, etc. A reusable and robust environment for verification is needed to improve the efficiency and quality of verification. In this paper, we present a series of research works, including what kinds of simulation techniques should be used and which methodology should be addressed. By using the Universal Verification Methodology (UVM) template, the verification modeling is done by us, and verification code is generated with FPGA automatic simulation tool (SunwiseFAS). the performance of this tool on automatic constructing simulation environment is presented, too.

关键词： Schedules Space missions Tools logic gates Task analysis field programmable gate arrays

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FPGA based Hybrid Random Number Generators

FPGA based Hybrid Random Number Generators

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international conference of Electronics, Communication and Aerospace Technology (ICECA)

作者： G.R. MahendraBabu K.P. Sridhar Baskar Karpagam Academy of Higher Education Coimbatore

ISBN: (数字)9781728163871

ISBN: (纸本)9781728163888

In this digital era, Pseudo-random number generators (PRNGs) are widely used in several real-time applications. As many types of PRNG are available, the feedback shift register method remains as the popular one. Despite the hype, these methods are unable to produce reliable data due to the presence of repetitive patterns in the sequence. this research work overcomes the aforementioned challenges by developing a hybrid technique. Entropy concept is used to improve the PRNGs quality. Since, Hybrid PRNGs pass in the testing, they can be implemented in real-time applications.

关键词： field programmable gate arrays Generators Hybrid power systems Testing Power demand logic gates Linear feedback shift registers

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Implementation of Bioimpedance Demodulator for Glottography

Implementation of Bioimpedance Demodulator for Glottography

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IEEE India conference (INDICON)

作者： Harikrishna Singapuri Aksh Patel Anand Darji Jignesh Sarvaiya S. V. National Institute of Technology Surat India

ISBN: (数字)9781728169163

ISBN: (纸本)9781728169170

With advancements in the field of medical science and instruments, it is essential that this payback to society. the primary diagnosis of change in body composition and clinical condition assessment can be made with the help of bioimpedance analysis. It is a cost-efficient and safe measurement of body composition. there are multiple ways to understand measured bioimpedance data. this paper reviews the embedded solution and FPGA implementation of bio-signal extraction for Impedance measurement for versatile physiological signal monitoring systems for healthcare applications. this paper focuses on the synchronous demodulation technique among various bio-impedance detection methods. the embedded solution is developed using Operational Amplifier, switches, and ADA2200 chip. Filtering is a crucial aspect of synchronous demodulation. thus FIR low-pass filter with direct form-II structure is used for FPGA implementation for less complicated architecture. Results show that the proposed design consumes less complex hardware and extracts bio-signal with acceptable noise levels.

关键词： Operational amplifiers Frequency modulation Low-pass filters Bioimpedance Hardware field programmable gate arrays Demodulation

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ZuCl: A ZynQ ultrascale+ framework for OpenCL HLS applications 5

ZuCl: A ZynQ ultrascale+ framework for OpenCL HLS applicatio...

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5th international Workshop on FPGAs for Software Programmers, FSP 2018, co-located with international conference on field programmable logic and applications, FPL 2018

作者： Pham, Khoa Dang Vaishnav, Anuj Vesper, Malte Koch, Dirk School of Computer Science University of Manchester Manchester United Kingdom

ISBN: (纸本)9783800747238

In this work, we are proposing the ZUCL framework for implementing and running OpenCL applications for the latest Xilinx ZYNQ UltraScale+ platform. ZUCL is a holistic framework addressing the FPGA OS infrastructure, high level synthesis (HLS) module implementation as well as the runtime management. ZUCL enables partial reconfiguration (PR) on this platform by providing an infrastructure featuring multiple adjacent PR regions having an identical resource layout. this allows users building their hardware modules once but instantiating them multiple times in the provided regions in a hot plug-and-play manner as well as implementing different sized modules that can share the reconfigurable resources. An automatic physical implementation backend based on templates allows implementing OpenCL kernels into hardware modules all the way from OpenCL descriptions to relocatable accelerator bitstreams in a fully software-centric design process. Finally, prototypes of generic device drivers for OpenCL kernels and a hardware task scheduler together with low-level configuration drivers have been developed to manage kernels at runtime. A demonstrator on a Xilinx ZCU102 evaluation board will show how multiple OpenCL kernels can be implemented and executed simultaneously with ease and flexibility by a ZYNQ UltraScale+ platform under direct control of the ARM SoC running Linux. © VDE VERLAG GMBH ∙ Berlin ∙ Offenbach

关键词： High level synthesis

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Accelerating Simulation for Agent-based Epidemic Models using FPGAs

Accelerating Simulation for Agent-based Epidemic Models usin...

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ACS/IEEE international conference on Computer Systems and applications

作者： Ce Guo Wayne Luk Stephen Weston Imperial College London UK Risk Advisory Group Deloitte UK

ISBN: (数字)9781728185774

ISBN: (纸本)9781728185781

Agent-based models (ABMs) play a critical role in the containment and mitigation of epidemics. An ABM for epidemics involves a population of agents that represent healthy and infected individuals. Users can simulate the interactions of the agents to analyse spreading patterns, make predictions and conduct what-if tests. A major drawback that limits the application of ABMs is the long simulation time for large populations. this paper proposes new techniques to speed up ABM-based simulation. Specifically, we present an agent-based model for epidemic spreading that enables effective acceleration using reconfigurable hardware. the key idea is to compute the infection probability in a novel way so that the amount of on-chip memory usage is independent of the population size. Also, we propose a parameter pre-computation algorithm, a parallel simulation algorithm and an efficient collaboration method between the host computer and the accelerator. We simulate the proposed model on an Intel Arria 10 FPGA and compare it with a software reference that simulates a conventional ABM on an Intel Core i5-9400F CPU with six cores. the two systems produce similar results, but the FPGA-based system achieves 14 times speedup compared to the software reference.

关键词： Computational modeling Statistics Sociology Epidemics System-on-chip Clustering algorithms field programmable gate arrays

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FPGA virtualization deployment based on Docker container technology

FPGA virtualization deployment based on Docker container tec...

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international conference on Mechanical, Control and Computer Engineering (ICMCCE)

作者： Xiangmeng Long Baohua Liu Feng Jiang Qingjie Zhang Xiaoli Zhi School of Computer Engineering and Science Shanghai University Shanghai China

FPGA (field programmable Gate Array) has special advantages in low latency, low power consumption and reconfigurable hardware as compared with CPU and GPU. It is deployed as heterogeneous accelerators on a large scale in cloud computing centers and research laboratories. Usually., developers operate directly on the physical machines and use the FPGA card exclusively. this leads to a bad utilization of FPGA resources. this paper proposes to virtualize and deploy FPGA resources as lightweight containers by using Docker and Kubernetes together. the Docker containers abstract FPGA resources and provide an isolated runtime environment for each application. the Kubernetes performs unified and automated scaling and scheduling of virtualized FPGA containers. thus, FPGA resources can be safely and effectively shared among multiple local and remote applications. Experiments show that the utilization of FPGA resources has been improved.

关键词： Runtime environment Cloud computing Power demand Laboratories Graphics processing units Containers logic gates

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FLS-Based Collision Avoidance Cyber Physical System for Warehouse Robots using FPGA 6

FLS-Based Collision Avoidance Cyber Physical System for Ware...

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6th international conference on Dependable Systems and their applications, DSA 2019

作者： Ahmed, Hossam O. Kuwait Kuwait

ISBN: (纸本)9781728160573

the overperforming enormous number of Automated Guided Vehicles (AGV) that have been adopted in warehouses recently proved their capabilities of speeding up the parcel exchange process in comparing with human capabilities. In order to increase the overall performance of these AGVs, we introduced an Artificial Intelligence (AI) based processing unit for the purpose of enhancing the collaborative diagnostics and decision making in such applications by exchanging feedback data frames to the center hub. the proposed AI-based controller is based on a multi-core Fuzzy logic System (FLS) is to differentiate the level of collision probability in a Cyber Physical System (CPS) using asymmetric data bus width architecture. the proposed systolic FLS architecture in this paper has been designed using VHDL to be interfaced with a three TFmini Plus Lidar Sensors and three MaxSonar ultrasonic sensors using the Intel Altera OpenVINO FPGA board. the proposed systolic FLS processing unit achieved a processing computational speed of about 14.36 GOPS at maximum operating frequency of 270.86 MHz while consuming about 58.56 mW as a core dynamic thermal power dissipation and around 28.38 mW as a 1/0 thermal power dissipation. © 2020 IEEE.

关键词： field programmable gate arrays (FPGA)

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Hidden Fault Analysis of FPGA Projects for Critical applications

Hidden Fault Analysis of FPGA Projects for Critical Applicat...

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international conference on Modern Problems of Radio Engineering, Telecommunications and Computer Science

作者： Oleksandr Drozd Ihor Perebeinos Oleksandr Martynyuk Kostiantyn Zashcholkin Olena Ivanova Myroslav Drozd Institute of Computer Systems Odesa National Polytechnic University Odesa Ukraine

ISBN: (数字)9781728155661

ISBN: (纸本)9781728155678

this paper focuses on the problem of hidden faults, which is seen like a growth one inherent in modern safety-related systems. the special feature of these is the designing for operation in two modes: normal and emergency. Digital components can accumulate hidden failures over a long-term normal mode. this reduces their fault tolerance and functional safety of the system in the most responsible emergency mode. Two conditions for occurrence of the hidden fault problem as a growth one are considered in view of a resource approach, which in the development of models, methods and means highlights levels of replication and diversification. Safety-related systems are analyzed as computer systems that have increased to the level of diversification to address the security challenge. their components are still stamped at a level of resource replication using matrix structures to process data in parallel codes. Fault-tolerant solutions become fault-safe with a sufficient level of circuit checkability, which is commonly known as testability, i.e. structural checkability, depending only on the structure of the circuit. In the operating mode, the checkability becomes structurally-functional, and in critical applications it is converted into a dual-mode, the shortage of which causes the hidden fault problem. A method of analyzing circuits for the possibility of hidden faults is suggested. the method is illustrated on example of an iterative array multiplier implemented in an FPGA project with a LUT-oriented architecture. A program model for the resulting scheme has been developed and potentially dangerous points have been found in it in which the hidden fault problem of may manifest itself.

关键词： fault diagnosis fault tolerance field programmable gate arrays integrated circuit reliability logic design multiplying circuits safety table lookup field programmable gate arrays Multiplying circuits Fault tolerance Table lookup integrated circuit reliability logic design Fault diagnosis safety faults FAILURE ANALYSIS

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Novel Synthesizable eFPGA based on Island Network with Multilevel Switch Boxes

Novel Synthesizable eFPGA based on Island Network with Multi...

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ACS/IEEE international conference on Computer Systems and applications

作者： Hajer Saidi Mariem Turki Zied Marrakchi Abdulfattah Obeid Mohamed Abid CES Research Laboratory National Engineering School of Sfax Digital Research center of Sfax (CRNS) Sfax Sfax Tunisia CES Research Laboratory National Engineering School of Sfax Sfax Tunisia National Center for Electronics and Photonics Technology King Abdulaziz City for Science and Technology Riyadh Riyadh Saudi Arabia

ISBN: (数字)9781728185774

ISBN: (纸本)9781728185781

Flexibility, low latency, energy-efficiency, and low area, power, and cost are very important to consider for hardware and software implementation of VLSI circuits. With the advanced technology used to design these circuits especially the System on Chip, embedded FPGA (eFPGA) is one of the fields that has attracted extensive attention to ensure flexibility into SoC. Matrix and hierarchical architectures are the two most popular architectures used to design an FPGA. this paper present firstly an embedded FPGA with hierarchical architecture, the configuration of this eFPGA is ensured by a loader with a proposed model. then, we propose the first embedded FPGA having a matrix architecture with a multi-level switch box. With the best of our knowledge, this is the first work that presents a decoder which loads the bitstream words to eFPGA SRAMs cells for the mesh of cluster architectures. A series of experimentation is conducted to evaluate the proposed eFPGAs. the static power, latency, and hardware utilization, as well as hardware implementation, are discussed and analyzed. Mesh of cluster eFPGA introduces an area overhead ≈ 2 times of tree eFPGA size which is correlated to static power but has a straightforward benefit in terms of frequency and performance, regularity, and easy to implement.

关键词： field programmable gate arrays Switches Table lookup Hardware Topology Load modeling IP networks

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