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检索条件"任意字段=17th International Conference on Field Programmable Logic and Applications"

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Facilitating Easier Access to FPGAs in the Heterogeneous Cloud Ecosystems 28

Facilitating Easier Access to FPGAs in the Heterogeneous Clo...

引用

28th international conference on field programmable logic and applications (FPL)

作者： Minhas, Umar Ibrahim Woods, Roger Karakonstantis, Georgios Queens Univ Belfast Belfast Antrim North Ireland

ISBN: (数字)9781538685174

ISBN: (纸本)9781538685174

With FPGAs being increasingly integrated into existing software-based heterogeneous cloud environments, novel evaluation mechanisms are required to reveal the energy performance trade-offs of accelerators (FPGAs, GPUs, etc) in high-level heterogeneous programming environments. For FPGAs, this involves also a reconsideration of scheduling policies and reconfiguration methods with an aim of integrating software based approaches as well as performance optimizations for wider workload sizes. the approaches are evaluated using various reconfiguration methodologies for a number of applications.

关键词： Task analysis field programmable gate arrays Graphics processing units Cloud computing Optimization Computational modeling throughput

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Enabling Low Impact, Rapid Debug for Highly Utilized FPGA Designs 28

Enabling Low Impact, Rapid Debug for Highly Utilized FPGA De...

引用

28th international conference on field programmable logic and applications (FPL)

作者： Hale, Robert Hutchings, Brad Brigham Young Univ Provo UT 84602 USA

ISBN: (数字)9781538685174

ISBN: (纸本)9781538685174

Inserting soft logic analyzers into FPGA circuits is a common way to provide signal visibility at run-time, helping users locate bugs in their designs. However, this can become infeasible for highly (70-90+%) utilized designs, which leave few logic resources or block RAMs available for internal logic analyzers. this paper presents a fast, low-impact method of enabling signal visibility in these situations using LUT-based distributed memory. Trace-buffers are inserted post-PAR allowing users to quickly change the set of observed nets. Results from routing-based experiments are presented which demonstrate that, even in highly utilized designs, many design signals can be observed with this technique.

关键词： Tools field programmable gate arrays Probes Table lookup Debugging Routing

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Multi-Fidelity Optimization for High-Level Synthesis Directives 28

Multi-Fidelity Optimization for High-Level Synthesis Directi...

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28th international conference on field programmable logic and applications (FPL)

作者： Lo, Charles Chow, Paul Univ Toronto Dept Elect & Comp Engn Toronto ON Canada

ISBN: (数字)9781538685174

ISBN: (纸本)9781538685174

High-Level Synthesis (HLS) tools enable rapid hardware development, but design expertise and effort are necessary to tune the high-level descriptions into optimized circuits. To improve designer productivity, automated design-space exploration techniques have been proposed. However, the optimization processes sample expensive CAD flows. In this paper, we adapt multi-fidelity optimization methods to incorporate low-fidelity estimates available in the FPGA CAD flow and speed up tuning of HLS parameters. We find that multi-fidelity optimization techniques can significantly reduce optimization time compared to previous approaches.

关键词： Optimization Solid modeling Clocks Tools Computational modeling field programmable gate arrays Hardware

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An Application-Specific field-programmable Tree Ensemble Architecture 28

An Application-Specific Field-Programmable Tree Ensemble Arc...

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28th international conference on field programmable logic and applications (FPL)

作者： Kuehn, Jan Manoli, Yiannos Univ Freiburg IMTEK Dept Microsyst Engn Freiburg Germany

ISBN: (数字)9781538685174

ISBN: (纸本)9781538685174

Supervised machine learning for data classification is increasingly implemented in hardware to be integrated close to the source of the data. the ability to update a trained machine learning model is the most important property any classification system must fulfill. this is often achieved by implementing the algorithm on reconfigurable hardware but some applications require speed, size, or power efficiency only application-specific integrated circuits (ASICs) can offer. Architectures that have proven to be very efficient on reconfigurable hardware are not always suited for custom ASIC designs. We therefore propose to integrate commonly used field-programmable technology in an application-specific architecture to allow updates of the trained model. this design pattern allows deep integration into full custom ASICs while leveraging all advantages of reconfigurable hardware.

关键词： Vegetation Integrated circuit modeling field programmable gate arrays Parallel architectures Hardware Decision trees

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A Novel TDC Scheme: Combinatorial Gray Code Oscillator Based TDC for Low Power and Low Resource Usage applications 5

A Novel TDC Scheme: Combinatorial Gray Code Oscillator Based...

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5th international conference on Event-Based Control, Communication, and Signal Processing (EBCCSP)

作者： Wu, Jinyuan Xu, Jingjing Fermilab Natl Accelerator Lab Batavia IL 60510 USA Purdue Univ 610 Purdue Mall W Lafayette IN 47907 USA

ISBN: (纸本)9781728123226

In common digital electronics design practice, combinatorial loop is less preferable, especially in the multi-bit cases. An exception of multi-bit feedback system that is allowed to be implemented in combinatorial loop is the Gray code sequence generator. the Gray code sequence generator runs by itself without being driven by an external clock. It steps through Gray code sequence significantly faster than the Gray code counter under the same silicon technology. In high energy physics experiments, it is necessary to find a low resource usage and low power TDC (Time-to-Digital-Converter) scheme for high channel count detectors. A Gray code oscillator based TDC is a good candidate for such a scheme. In this paper, we describe our work of design and implementation of a TDC based on combinatorial Gray code oscillator in a Xilinx Kintex-7 FPGA (field-programmable Gate Array). the implementation and test results are presented. the test result shows that the TDC using only 8 logic elements is able to reach a RMS precision of 160 ps for time difference measurements of a single pulse. the single pulse measurement precision can be further improved to 51 ps with the weighted average scheme using data from the same TDC channels captured by 4 consecutive system clock edges.

关键词： Time to Digital Converter Gray Code Oscillator FPGA applications

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Placement Strategies for 2.5D FPGA Fabric Architectures 28

Placement Strategies for 2.5D FPGA Fabric Architectures

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28th international conference on field programmable logic and applications (FPL)

作者： Ravishankar, Chirag Gaitonde, Dinesh Bauer, Trevor Xilinx Inc 3100 Logic Dr Longmont CO 80503 USA Xilinx Inc 2100 Logic Dr San Jose CA USA

ISBN: (数字)9781538685174

ISBN: (纸本)9781538685174

FPGAs take advantage of 2.5D stacking technology to manufacture large capacity and high performance heterogenous devices at reasonable costs. EDA tools need to be aware of and exploit physical characteristics of such devices, for example the reduced connection count between SLRs, the infrequency of SLL channel occurence in the fabric, and the aspect ratios of individual SLRs. We implement a partition driven placer to explore various EDA options to take advantage of architectural features in 2.5D FPGAs. We improve the routability of designs by optimizing the placer for discrete SLL channels and reduced connection counts. We propose a cut schedule for the partitioner to orient the placement with awareness of the aspect ratio of SLRs to improve track demands within each SLR.

关键词： field programmable gate arrays Routing Stacking Wires Fabrics Complexity theory Heating systems

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Multipumping-Enabled Multiported SRAM Based Efficient TCAM Design

Multipumping-Enabled Multiported SRAM Based Efficient TCAM D...

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international conference on Electronics, Materials Engineering and Nano-Technology (IEMENTech)

作者： Ashwin Santhosh Sonali Agrawal Amrita School of Engineering Bengaluru Amrita Vishwa Vidyapeetham India

ISBN: (数字)9781728192871

ISBN: (纸本)9781728192888

Memory which is used for searching applications, like Network routers, operating at a higher speed is called Ternary Content Addressable Memory (TCAM). the requirement of TCAM is gradually growing in the searching field applications. TCAM memories are usually built in ASIC (Application Specific Integrated Circuit) which offers searching operation at a higher speed in a predetermined time but is expensive in cost. TCAMs designed on FPGAs (field programmable Gate Array) experience high power consumption, larger use of FPGA resources, and suffer from the inefficiency of storage. TCAM using multipumping and multiported SRAM is designed for achieving an effectual use of FPGA resources, and a reduction in usage of power and area. In the present SRAM based TCAM designs, there is an exponential growth in memory usage due to the increase in the patterns of TCAM, which is reduced by cascading the multiple blocks of SRAM (BRAMs) in FPGA that makes growth linear. BRAMs of FPGAs have restrictions in depth, which restricts the effectual storage of TCAM bits. In this paper, a modified TCAM design is proposed which avoids this restriction by using shallow sub-blocking of BRAMs. the design proposed in this paper operates the multiported SRAM by using the dual-port BRAM and by clocking it internally at a higher frequency using multipumping technique which allows access of the BRAM subblocks in one cycle of the system clock. these modifications in the divisional traditional TCAM table results in an effectual design of TCAM memory. the proposed design is coded in Verilog and simulated using the Xilinx ISE tool and was implemented on a Virtex 7xc7vx485 FPGA device. the proposed design has better performance, in terms of 26% reduction in power and 7% reduction in area, as compared to existing SRAM based TCAM design.

关键词： Random access memory field programmable gate arrays Clocks logic gates Multiplexing Memory management Associative memory

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Stealthy-Shutdown: Practical Remote Power Attacks in Multi - Tenant FPGAs

Stealthy-Shutdown: Practical Remote Power Attacks in Multi -...

引用

IEEE international conference on Computer Design: VLSI in Computers and Processors, (ICCD)

作者： Yukui Luo Cheng Gongye Shaolei Ren Yunsi Fei Xiaolin Xu Northeastern University MA USA University of California Riverside CA USA

ISBN: (数字)9781728197104

ISBN: (纸本)9781728197111

With the deployment of artificial intelligent (AI) algorithms in a large variety of applications, there creates an increasing need for high-performance computing capabilities. As a result, different hardware platforms have been utilized for acceleration purposes. Among these hardware-based accelerators, the field-programmable gate arrays (FPGAs) have gained a lot of attention due to their re-programmable characteristics, which provide customized control logic and computing operators. For example, FPGAs have recently been adopted for on-demand cloud services by the leading cloud providers like Amazon and Microsoft, providing acceleration for various compute-intensive tasks. While the co-residency of multiple tenants on a cloud FPGA chip increases the efficiency of resource utilization, it also creates unique attack surfaces that are under-explored. In this paper, we exploit the vulnerability associated with the shared power distribution network on cloud FPGAs. We present a stealthy power attack that can be remotely launched by a malicious tenant, shutting down the entire chip and resulting in denial-of-service for other co-located benign tenants. Specifically, we propose stealthy-shutdown: a well-timed power attack that can be implemented in two steps: (1) an attacker monitors the realtime FPGA power-consumption detected by ring-oscillator-based voltage sensors, and (2) when capturing high power-consuming moments, i.e., the power consumption by other tenants is above a certain threshold, she/he injects a well-timed power load to shut down the FPGA system. Note that in the proposed attack strategy, the power load injected by the attacker only accounts for a small portion of the overall power consumption; therefore, such attack strategy remains stealthy to the cloud FPGA operator. We successfully implement and validate the proposed attack on three FPGA evaluation kits with running real-world applications. the proposed attack results in a stealthy-shutdown, demonstratin

关键词： Power demand Tools threshold voltage Sensors Acceleration Task analysis field programmable gate arrays

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A Smart Network Interface Approach for Distributed applications on Xilinx Zynq SoCs 28

A Smart Network Interface Approach for Distributed Applicati...

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28th international conference on field programmable logic and applications (FPL)

作者： Shreejith, Shanker Cooke, Ryan A. Fahmy, Suhaib A. Univ Warwick Sch Engn Coventry W Midlands England

ISBN: (数字)9781538685174

ISBN: (纸本)9781538685174

Networked embedded systems have seen tremendous growth with many more complex critical and non-critical systems exchanging information over networks of various types. At each node, information is processed by the network stack before the application sees the data. Large portions of the stack are in software, resulting in significant and non-deterministic delays. While hybrid compute platforms like the Xilinx Zynq can accelerate processing tasks through offloading to programmable logic, the delays incurred due to connectivity can significantly impact overall application latency. In this paper, we present a smart network interface approach for the Xilinx Zynq platform based on datapath extensions within the otherwise standard Ethernet interface. We show that this approach improves computation offload latency by 24-27% and throughput by 37% for a complex computational kernel.

关键词： Ethernet Network interfaces Hardware Random access memory Software Registers Monitoring

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field programmable Gate Array Hardware Accelerator of Prime Implicants Generation for Single-Output Boolean Functions Minimization

Field Programmable Gate Array Hardware Accelerator of Prime ...

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international conference on Emerging eLearning Technologies and applications (ICETA)

作者： B. Madoš Z. Bilanová E. Chovancová N. Ádám Department of Computers and Informatics Faculty of Electrical Engineering and Informatics Technical University of Košice Košice Slovak

ISBN: (数字)9781728149677

ISBN: (纸本)9781728149684

the paper deals with the problematics of two-level single-output Boolean functions minimization which is important for many fields of science and technology including logic and control systems design, software engineering, artificial intelligence and others. In this work proposed solution, which is aimed to the production of prime implicants for particular Boolean functions, as the first step of Boolean functions minimization, is based on the use of designed hardware accelerator using field programmable Gate Array (FPGA) technology. As the part of this work, input and output binary vectors encoding is proposed along with the combinational logic module, described using VHDL. Module is implemented into Xilinx Kintex-7 FPGA KC705 Evaluation Kit evaluation board. Advantage of proposed hardware accelerator is in extremely small time complexity in comparison to the algorithms which are utilizing classical CPU based solutions. Another advantage is in constant time of prime implicants generation in case of the same number of input variables of Boolean function regardless of ON set cardinality. Disadvantage of the solution is that it is not possible to define don't care set and in space complexity which is rising quickly according to the number of input variables of Boolean function.

关键词： Boolean functions logic gates Hardware Minimization Input variables Encoding field programmable gate arrays

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