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检索条件"任意字段=17th International Conference on Field Programmable Logic and Applications"

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field programmable Gate Array Hardware Accelerator of Prime Implicants Generation for Single-Output Boolean Functions Minimization

Field Programmable Gate Array Hardware Accelerator of Prime ...

引用

international conference on Emerging eLearning Technologies and applications (ICETA)

作者： B. Madoš Z. Bilanová E. Chovancová N. Ádám Department of Computers and Informatics Faculty of Electrical Engineering and Informatics Technical University of Košice Košice Slovak

ISBN: (数字)9781728149677

ISBN: (纸本)9781728149684

the paper deals with the problematics of two-level single-output Boolean functions minimization which is important for many fields of science and technology including logic and control systems design, software engineering, artificial intelligence and others. In this work proposed solution, which is aimed to the production of prime implicants for particular Boolean functions, as the first step of Boolean functions minimization, is based on the use of designed hardware accelerator using field programmable Gate Array (FPGA) technology. As the part of this work, input and output binary vectors encoding is proposed along with the combinational logic module, described using VHDL. Module is implemented into Xilinx Kintex-7 FPGA KC705 Evaluation Kit evaluation board. Advantage of proposed hardware accelerator is in extremely small time complexity in comparison to the algorithms which are utilizing classical CPU based solutions. Another advantage is in constant time of prime implicants generation in case of the same number of input variables of Boolean function regardless of ON set cardinality. Disadvantage of the solution is that it is not possible to define don't care set and in space complexity which is rising quickly according to the number of input variables of Boolean function.

关键词： Boolean functions logic gates Hardware Minimization Input variables Encoding field programmable gate arrays

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A Demo of FPGA Aggressive Voltage Downscaling: Power and Reliability Tradeoffs 28

A Demo of FPGA Aggressive Voltage Downscaling: Power and Rel...

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28th international conference on field programmable logic and applications (FPL)

作者： Salami, Behzad Unsal, Osman Cristal, Adrian BSC Barcelona Spain UPC Barcelona Spain

ISBN: (数字)9781538685174

ISBN: (纸本)9781538685174

the power consumption of digital circuits, e.g., field programmable Gate Arrays (FPGAs), is directly related to their operating supply voltages. On the other hand, usually, chip vendors introduce a conservative voltage guardband below the standard nominal level to ensure the correct functionality of the design in worst-case process and environmental scenarios. For instance, this voltage guardband is empirically measured to be 12%, 20%, and 16% of the nominal level in commercial CPUs [1], Graphics Processing Units (GPUs) [2], and Dynamic RAMs (DRAMs) [3], respectively. However, in many real-world applications, this guardband is extremely conservative and eliminating it can result in significant power savings without any overhead. Motivated by these studies, we aim to extend the undevolting technique to commercial FPGAs. Toward this goal, we will practically demonstrate the voltage guardband for a representative Xilinx FPGA, with a preliminary concentration on on-chip memories, or Block RAMs (BRAMs).

关键词： field programmable gate arrays Random access memory Voltage control Reliability Voltage measurement System-on-chip Circuit faults

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Revisiting FPGA Implementation of Montgomery Multiplier in Redundant Number System for Efficient ECG applications in GF(p) 28

Revisiting FPGA Implementation of Montgomery Multiplier in R...

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28th international conference on field programmable logic and applications (FPL)

作者： Roy, Debapriya Basu Mukhopadhyay, Debdeep Indian Inst Technol Kharagpur Dept Comp Sci & Engn Kharagpur W Bengal India

ISBN: (数字)9781538685174

ISBN: (纸本)9781538685174

the fast implementations of ECC in GF(p) are generally implemented using specialized prime field, and henceforth, they are dependent on the structure of the prime. But, these implementations cannot be ported to generic curves which do not support such prime structures. Such generic curves are often used in various crypto-applications like pairing and post quantum secure supersingular isogeny based key exchange. In those cases, modular multiplication is executed through Montgomery multiplier which is slower compared to modular multiplication using specialized primes. this work aims to reduce the speed gap between Montgomery multiplication and modular multiplication in specialized prime field by presenting an efficient implementation of Montgomery multiplier on FPGA using the redundant number system.

关键词： Montgomery multiplier Redundant number system ECC

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Nonvolatile Binary CNN Accelerator with Extremely Low Standby Power using RRAM for IoT applications 13

Nonvolatile Binary CNN Accelerator with Extremely Low Standb...

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13th IEEE international conference on ASIC

作者： Cai, Yujie Zhou, Keji Xue, Xiaoyong Wang, Mingyu Zeng, Xiaoyang Fudan Univ State Key Lab ASIC & Syst Shanghai 201203 Peoples R China

ISBN: (纸本)9781728107356

Recently, with the development of 5G communications technology, a fully interconnected world is coming. Because 5G has the characteristics of low power consumption, high speed, low cost and small delay, the change brought to the Internet of things industry is dramatic [1]. Artificial intelligence technology has great potential in the field of IoT devices, but the huge computational complexity makes it difficult to be realized on a power-critical device. In this paper, we demonstrate a nonvolatile binary convolutional neural network accelerator. the main contributions of this work are summarized as follows: (1) A nonvolatile binary CNN data path based on RRAM, which can be fully power-gated in standby state;(2) the matrix multiplication and addition is performed by RRAM other than digital logic, with the binary weights stored in the RRAM;(3) Since the accelerator can be fully powered down, the power dissipated during the standby state is almost zero.

关键词： RRAM

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Resource Elastic Virtualization for FPGAs using OpenCL 28

Resource Elastic Virtualization for FPGAs using OpenCL

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28th international conference on field programmable logic and applications (FPL)

作者： Vaishnav, Anuj Khoa Dang Pham Koch, Dirk Garside, James Univ Manchester Sch Comp Sci Manchester Lancs England

ISBN: (数字)9781538685174

ISBN: (纸本)9781538685174

FPGAs are rising in popularity for acceleration in all kinds of systems. However, even in cloud environments, FPGA devices are typically still used exclusively by one application only. To overcome this, and as an approach to manage FPGA resources with OS functionality, this paper introduces the concept of resource elastic virtualization which allows shrinking and growing of accelerators in the spatial domain with the help of partial reconfiguration. With this, we can serve multiple applications simultaneously on the same FPGA and optimize the resource utilization and consequently the overall system performance. We demonstrate how an implementation of resource elasticity can be realized for OpenCL accelerators along with how it can achieve 23x better FPGA utilization and 49% better performance on average while simultaneously lowering waiting time for tasks.

关键词： field programmable gate arrays Task analysis Hardware Virtualization Resource management Elasticity Layout

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A High Performance Implementation of Quasi Delay Insensitive Booleans Functions 26

A High Performance Implementation of Quasi Delay Insensitive...

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IEEE 26th international conference on Electronics, Electrical Engineering and Computing (INTERCON)

作者： Oliveira, Duarte L. Verducci, Orlando Batista, Gracieth C. Curtinhas, Tiago S. Technol Inst Aeronaut ITA Elect Engn Div ILEA Sao Jose Dos Campos SP Brazil Adventist Univ Ctr Sao Paulo Unasp Dept Comp Sci Sao Paulo Brazil

ISBN: (纸本)9781728136462

Digital circuit design demands critical requirements such as power consumption, robustness, performance, etc. when it is implemented in VLSI (Very Large Scale Integration). the asynchronous paradigm presents interesting features aiming to solve these requirements. An important class of asynchronous paradigm is the so-called QDI (Quasi Delay Insensitive) circuits that can also be used for critical requirements design. QDI circuits are interesting for those kinds of applications because they are robust to noise, to temperature variations, to wire and gate delays and to supply voltage variation, having also low electromagnetic emissions. QDI combinational circuits are designed as function blocks whose indicatability shows the robustness of the circuit communication with the environment. this paper presents two architectures based on basic gates and C elements as also an approach to the synthesis of the QDI function blocks. the two new architectures were prototyped in FPGAs (field programmable Gated Array) devices, applied in a set of benchmarks and compared with other architectures of the literature. Our proposal shows respectively a gain of up to 18.6%, 53.1%, 40.7% and 51.8% in latency, number of LUTs and power, dynamic and static, respectively.

关键词： asynchronous logic QDI circuits dual-rail code

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Customizing Low-Precision Deep Neural Networks For FPGAs 28

Customizing Low-Precision Deep Neural Networks For FPGAs

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28th international conference on field programmable logic and applications (FPL)

作者： Faraone, Julian Gambardella, Giulio Boland, David Fraser, Nicholas Blott, Michaela Leong, Philip H. W. Univ Sydney Sydney NSW Australia Xilinx Res Labs Dublin Ireland

ISBN: (纸本)9781538685174

In this paper, we argue that instead of solely focusing on developing efficient architectures to accelerate well-known low-precision CNNs, we should also seek to modify the network to suit the FPGA. We develop a fully automative toolflow which focuses on modifying the network through filter pruning, such that it efficiently utilizes the FPGA hardware whilst satisfying a predefined accuracy threshold. Although fewer weights are removed in comparison to traditional pruning techniques designed for software implementations, the overall model complexity and feature map storage is greatly reduced. We implement the AlexNet and TinyYolo networks on the large-scale ImageNet and PascalVOC datasets, to demonstrate up to roughly 2x speedup in frames per second and 2x reduction in resource requirements over the original network, with equal or improved accuracy.

关键词： field programmable gate arrays Hardware Quantization (signal) throughput Memory management Neural networks

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Case for Fast FPGA Compilation using Partial Reconfiguration 28

Case for Fast FPGA Compilation using Partial Reconfiguration

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28th international conference on field programmable logic and applications (FPL)

作者： Park, Dongjoon Xiao, Yuanlong Magnezi, Nevo DeHon, Andre Univ Penn Dept Elect & Syst Engn Philadelphia PA 19104 USA

ISBN: (数字)9781538685174

ISBN: (纸本)9781538685174

Despite the FPGA's advantages over other hardware platforms, long compilation time prevents FPGA engineers from efficiently exploring the design space and discourages new users who want to quickly iterate for debugging. To reduce compilation time, this work adopts a divide-and-conquer approach using Partial Reconfiguration with a Packet-Switched Fat-Tree network. Partially reconfigured leaves in the packet-switched network are independent from each other and can be compiled separately in parallel. Also, when a minor fix is required to a bitstream, only the corresponding leaves need to be incrementally compiled. Preliminary experimental evidence from our work-in-progress effort illustrates how a 30 minute full-chip compile time can be reduced to 7 minutes.

关键词： field programmable gate arrays Table lookup Overlay networks Runtime Tools Hardware Standards

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Deterministic Parallel Routing for FPGAs based on Galois Parallel Execution Model 28

Deterministic Parallel Routing for FPGAs based on Galois Par...

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28th international conference on field programmable logic and applications (FPL)

作者： Moctar, Yehdhih Stojilovic, Mirjana Brisk, Philip IBM Res Austin TX 78758 USA Ecole Polytech Fed Lausanne Sch Comp & Commun Sci Lausanne Switzerland Univ Calif Riverside Riverside CA 92521 USA

ISBN: (数字)9781538685174

ISBN: (纸本)9781538685174

this paper describes a deterministic and parallel implementation of the VPR routability-driven router for FPGAs. We considered two parallefization strategies: (1) routing multiple nets in parallel;and (2) routing one net at a time, while parallelizing the Maze Expansion step. Using eight threads running on eight cores, the two methods achieved speedups of 1.84 x and 3.67 x, respectively, compared to VPR's single threaded routability-driven router. Removing the determinism requirement increased these respective speedups to 2.67 x and 5.46 x, while sacrificing the guarantee of reproducible results.

关键词： Routing Nickel Instruction sets field programmable gate arrays Runtime Parallel processing Task analysis

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A Survey on FPGA Virtualization 28

A Survey on FPGA Virtualization

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28th international conference on field programmable logic and applications (FPL)

作者： Vaishnav, Anuj Khoa Dang Pham Koch, Dirk Univ Manchester Sch Comp Sci Manchester Lancs England

ISBN: (数字)9781538685174

ISBN: (纸本)9781538685174

FPGA accelerators are being applied in various types of systems ranging from embedded systems to cloud computing for their high performance and energy efficiency. Given the scale of deployment, there is a need for efficient application development, resource management, and scalable systems, which make FPGA virtualization extremely important. Consequently, FPGA virtualization methods and hardware infrastructures have frequently been proposed in both academia and industry for addressing multi-tenancy execution, multi-FPGA acceleration, flexibility, resource management and security. In this survey, we identify and classify the various techniques and approaches into three main categories: 1) Resource level, 2) Node level, and 3) Multi-node level. In addition, we identify current trends and developments and highlight important future directions for FPGA virtualization which require further work.

关键词： field programmable gate arrays Virtualization Computer architecture Software Hardware Fabrics Task analysis

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