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检索条件"任意字段=17th International Conference on Field Programmable Logic and Applications"

共 1932 条记录，以下是371-380 订阅

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Median filtering with very large windows: SKA algorithms for FPGAs 28

Median filtering with very large windows: SKA algorithms for...

引用

28th international conference on field programmable logic and applications (FPL)

作者： Sherwin, Tyrone Wang, Kevin I-Kai thiagaraj, Prabu Sinnen, Oliver Univ Auckland Dept Elect & Comp Engn Auckland New Zealand Univ Manchester Manchester Lancs England Raman Res Inst Bangalore Karnataka India

ISBN: (数字)9781538685174

ISBN: (纸本)9781538685174

Large scale median filtering algorithms are investigated in the context of the Square Kilometre Array (SKA) pulsar search;a signal processing pipeline estimated to require more than 10POps on 60PB of search data collected per day. Real time performance is needed for rectangular median windows of 63 frequency channels across 1023 time steps, requiring at least 64 million values to be calculated and output per second. this paper proposes an algorithmic approach for large scale median filtering based on existing techniques, providing improvements for the heterogeneous system used and utilising a high-end FPGA accelerator. Taking advantage of OpenCL for rapid parameter sweeping, the design space was explored to find the best algorithmic approach. the evaluation results are promising and show output of up to 993 million values per second on an Arria-10 FPGA, coming close to the limits set by resources and bandwidth. these results are set into relation with GPU and CPU implementations for the same algorithm, taking advantage of the OpenCL portability, achieving up to 16.8 and 9.1Mvalue/s respectively.

关键词： Microsoft Windows Histograms field programmable gate arrays Signal processing algorithms Time-frequency analysis Loading Complexity theory

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An Efficient, Current-Mode Full-Adder Based on Majority logic in CNFET Technology

An Efficient, Current-Mode Full-Adder Based on Majority Logi...

引用

international econference on Computer and Knowledge Engineering (ICCKE)

作者： Mostafa Parvizi Sayed Mohammad Ali Zanjani Najafabad Branch Islamic Azad University Najafabad Iran Smart Microgrid Research Center Najafabad Branch Islamic Azad University Najafabad Iran

ISBN: (数字)9781728185668

ISBN: (纸本)9781728185675

In this study, a new high-speed low-power current-mode full-adder (CMFA) based on majority logic is presented. the proposed CMFA consists of only 14 transistors. Simulations are performed by HSPICE using the 32 nm carbon nanotube field-effect transistor (CNTFET) Stanford model at a supply voltage of 0.5 V, operating frequency of 1 GHz, a load capacitance of 2 fF and a current of 10 μA for any reference current value suitable for low-voltage high-speed applications. the simulation results show that, in the worst case, the delay of the proposed circuit for sum and carry outputs is equal to 42 ps, and the power-delay product (PDP) is 98.7 E -17 J.

关键词： CNTFETs Delays Transistors Adders Capacitance Simulation Propagation delay

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Application Partitioning on FPGA Clusters: Inference over Decision Tree Ensembles 28

Application Partitioning on FPGA Clusters: Inference over De...

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28th international conference on field programmable logic and applications (FPL)

作者： Owaida, Muhsen Alonso, Gustavo Swiss Fed Inst Technol Dept Comp Sci Syst Grp Zurich Switzerland

ISBN: (数字)9781538685174

ISBN: (纸本)9781538685174

In the same way multi-core and CPU clusters are used for large problems, multi-FPGA clusters are needed to tackle applications not fitting within a single FPGA, such as machine learning methods based on large models. Recent FPGA deployments in datacenters offer flexible pools of FPGAs that can be used in different configurations. In addition to those of a typical cluster architecture, FPGA clusters often have added capabilities such as being hosted by large server nodes (e.g., Amazon F1 Instance), or a network backbone directly connecting multiple FPGAs (e.g., Microsoft Catapult). While such designs open up many opportunities, mapping application logic onto a pool of FPGA resources is a non trivial task. It requires partitioning the application across multiple FPGAs, inter-FPGA communication management of multiple data stream classes, and balancing communication-computation bandwidth. In this paper, we explore and develop techniques for mapping a resource-intensive machine learning application, namely inference over decision tree ensembles on a datacenter-grade FPGA cluster. the FPGA cluster is built out of 20 Microsoft Catapult FPGA boards with a flexible inter-FPGA network topology. We developed a lightweight inter-FPGA communication protocol and routing layer to facilitate the communication between different parts of the application. Our evaluation provides insights on the overall performance benefits of the design and outlines some of the techniques needed to efficiently map applications onto a pool of distributed FPGAs.

关键词： field programmable gate arrays Servers Decision trees Distributed databases Bandwidth Machine learning Computer architecture

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Accelerated Wire-Speed Packet Capture at 200 Gbps 28

Accelerated Wire-Speed Packet Capture at 200 Gbps

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28th international conference on field programmable logic and applications (FPL)

作者： Kekely, Lukas Spinler, Martin Friedl, Stepan Sikora, Jiri Korenek, Jan CESNET Ale Zikova 4 Prague 16000 Czech Republic

ISBN: (数字)9781538685174

ISBN: (纸本)9781538685174

We present our latest FPGA acceleration card NFB-200G2QL that is specifically designed to enable traffic processing at 200 Gbps. Unique high-speed DMA engines in the FPGA together with highly optimized Linux drivers enable data transfer through PCIe interfaces with minimal CPU overhead. Captured traffic can be independently distributed between individual cores of two physical CPUs (NUMA nodes) without utilization of QPI. As a result, wire-speed packet capture to the host memory from two fully saturated 100 Gbps Ethernet interfaces (QSFP28+ cages) is achieved and various network monitoring applications can utilize the power of the latest FPGAs and CPUs for data processing. this is especially useful when both directions of a single 100GbE link are monitored. the live demonstration shows how the packets are received from two 100 Gbps Ethernet links at wire-speed and captured to the host memory at 200 Gbps without a loss. the opposite direction of communication is also shown, i.e. how the packets are transmitted from the host memory and fully saturate the two 100GbE network interfaces. Achieved speeds are demonstrated by counters and gauges showing generated, received/transmitted and captured packets. We also show statistics of CPU load during the packet capture/transmission for different packet lengths.

关键词： field programmable gate arrays Ethernet throughput Data transfer Standards Acceleration Monitoring

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A FPGA Accelerator for Real-Time 3D Non-Rigid Registration Using Tree Reweighted Message Passing and Dynamic Markov Random field Generation 28

A FPGA Accelerator for Real-Time 3D Non-Rigid Registration U...

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28th international conference on field programmable logic and applications (FPL)

作者： Barrow, Michael Burns, Steven M. Kastner, Ryan Univ Calif San Diego La Jolla CA 92093 USA Intel Corp Hillsboro OR 97124 USA

ISBN: (数字)9781538685174

ISBN: (纸本)9781538685174

Non-rigid 3D registration is a technique for matching 3D scans of a scene involving deformable objects. Augmented reality, gesture recognition, medical imaging, and many other computer vision and graphics applications require realtime registration to model deformable or articulated objects. Unfortunately, non-rigid registration is a computationally intensive problem that requires careful optimization to maximize throughput and latency. We present a FPGA+CPU accelerator for real-time non-rigid 3D registration based on Tree Reweighted Message Passing (TRW-S). We overcome memory bound issues and scheduling limitations of conventional TRW-S by dynamically generating the Markov Random fields. this, along with a bevy of other architectural optimizations, allows us to almost saturate 1024 multipliers in a Arria 10 at 100MHz. We achieve a 600x speed up over baseline TRW-S and our registration architecture has up to 81x energy reduction over a software implementation of our algorithm. We demonstrate the performance of our system by performing real-time (20 scan per second) registration on a complicated surgical scene.

关键词： field programmable Gate Array (FPGA) 3D Non-Rigid Registration Sequential Tree Reweighted Message Passing (TRW-S) Dynamic Markov Random field (MRF)

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Towards Efficient Convolutional Neural Network for Domain-Specific applications on FPGA 28

Towards Efficient Convolutional Neural Network for Domain-Sp...

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28th international conference on field programmable logic and applications (FPL)

作者： Zhao, Ruizhe Ng, Ho-Cheung Luk, Wayne Niu, Xinyu Imperial Coll London Dept Comp London England Corerain Technol Ltd Shenzhen Peoples R China

ISBN: (数字)9781538685174

ISBN: (纸本)9781538685174

FPGA becomes a popular technology for implementing Convolutional Neural Network (CNN) in recent years. Most CNN applications on FPGA are domain-specific, e.g., detecting objects from specific categories, in which commonly used CNN models pre-trained on general datasets may not be efficient enough. this paper presents TuRF, an end-to-end CNN acceleration framework to efficiently deploy domain-specific applications on FPGA by transfer learning that adapts pre-trained models to specific domains, replacing standard convolution layers with efficient convolution blocks, and applying layer fusion to enhance hardware design performance. We evaluate TuRF by deploying a pre-trained VGG-16 model for a domain-specific image recognition task onto a Stratix V FPGA. Results show that designs generated by TuRF achieve better performance than prior methods for the original VGG-16 and ResNet-50 models, while for the optimised VGG-16 model TuRF designs are more accurate and easier to process.

关键词： Convolution field programmable gate arrays Standards Hardware Acceleration Task analysis Kernel

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Providing Multi-tenant Services with FPGAs: Case Study on a Key-Value Store 28

Providing Multi-tenant Services with FPGAs: Case Study on a ...

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28th international conference on field programmable logic and applications (FPL)

作者： Istvan, Zsolt Alonso, Gustavo Singla, Ankit Swiss Fed Inst Technol Dept Comp Sci Syst Grp Zurich Switzerland

ISBN: (数字)9781538685174

ISBN: (纸本)9781538685174

FPGAs can be used to speed up computation and data management tasks in various application domains. In cloud settings, however, high utilization is as important as high performance. In software it is common to co-locate different tenants' workloads on the same servers to increase utilization. Sharing an FPGA is more complex because applications take up physical space on the chip. Even though it is possible to physically partition the FPGA, tenants can have widely different requirements and their needs can also fluctuate over time. In this paper, we take a different approach and provide flexibility to the tenants who are interested in the same type of application but have different workloads and quality of service requirements. We demonstrate our approach of multi-tenant design using a key value store service but the ideas generalize to other network facing services as well. A key challenge of multi-tenancy is to efficiently share the underlying hardware while enforcing strict data and performance isolation between tenants. In this paper we demonstrate that, by following a single-pipeline design principle, it is possible to control each tenant's share of network bandwidth and computational resources even for complex, distributed operations. Furthermore, we show how state-machine based logic on the FPGA can be made tenant-aware without introducing significant context-switching overhead. Finally, our hardware design provides flexibility for changing per-tenant shares, allowing the same circuit to be used by one or multiple tenants without performance loss.

关键词： field programmable gate arrays Pipelines Bandwidth Cloud computing Data structures Switches Resource management

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FlueNT10G: A programmable FPGA-based Network Tester for Multi-10-Gigabit Ethernet 28

FlueNT10G: A Programmable FPGA-based Network Tester for Mult...

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28th international conference on field programmable logic and applications (FPL)

作者： Oeldemann, Andreas Wild, thomas Herkersdorf, Andreas Tech Univ Munich Chair Integrated Syst Munich Germany

ISBN: (数字)9781538685174

ISBN: (纸本)9781538685174

We present FlueNT10G, an open-source FPGAbased network tester for precise replay of network traces, as well as for accurate packet capture and round-trip latency measurements. FlueNT1OG streams replay and capture data between the host system and the FPGA board during active tests. It enables continuous measurements without being constrained by the memory capacity of the FPGA board. FlueNT1OG is able to concurrently replay and capture traffic on three 10 Gbit/s network interfaces for all packet sizes. When operated exclusively in replay or capture mode, throughput increases to 4x 10 Gbit/s. Our design yields a temporal resolution of 6.4 ns for precise traffic pattern generation, as well as for accurate arrival timestamping and latency measurements. On the software-side, F1ueNT1OG is complemented by an API enabling the programmable execution of reproducible network measurements. Targeting the automated performance evaluation of different virtualized network function configurations, the API further integrates access to a bidirectional side-band channel for device-under-test reconfiguration and status feedback. FlueNT1OG has been implemented on the NetFPGA-SUME platform (Xilinx Virtex-7 XC7VX690T) with an FPGA resource utilization of no more than 25%, which leaves sufficient capacity available for future design extensions.

关键词： network tester packet generator packet capture latency measurement FPGA measurement automation

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A Demonstration of FPGA-based You Only Look Once version2 (YOLOv2) 28

A Demonstration of FPGA-based You Only Look Once version2 (Y...

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28th international conference on field programmable logic and applications (FPL)

作者： Nakahara, Hiroki Shimoda, Masayuki Sato, Shimpei Tokyo Inst Technol Tokyo Japan

ISBN: (数字)9781538685174

ISBN: (纸本)9781538685174

We implement the YOLO (You only look once) object detector on an FPGA, which is faster and has higher accuracy. It is based on the convolutional deep neural network (CNN), and it is a dominant part of both the performance and the area. It is widely used in the embedded systems, such as robotics, autonomous driving, security, and drones, all of which require high-performance and low-power consumption. A frame object detection problem consists of two problems: one is a regression problem to spatially separated bounding boxes, the second is the associated classification of the objects within realtime frame rate. We used the binary (1 bit) precision CNN for feature extraction and the half-precision (16 bit) precision CNN for both classification and localization. We implement a pipelined based architecture for the mixed-precision YOLOv2 on the Xilinx Inc. zcul02 board, which has the Xilinx Inc. Zynq Ultrascale+ MPSoC. the implemented object detector archived 35.71 frames per second (FPS), which is faster than the standard video speed (29.9 FPS). Compared with a CPU and a GPU, an FPGA based accelerator was superior in power performance efficiency. Our method is suitable for the frame object detector for an embedded vision system.

关键词： field programmable gate arrays Computer architecture Graphics processing units Detectors Feature extraction Training Neural networks

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Reconfigurable Acceleration of 3D-CNNs for Human Action Recognition with Block Floating-Point Representation 28

Reconfigurable Acceleration of 3D-CNNs for Human Action Reco...

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28th international conference on field programmable logic and applications (FPL)

作者： Fan, Hongxiang Ng, Ho-Cheung Liu, Shuanglong Que, Zhiqiang Niu, Xinyu Luk, Wayne Imperial Coll London Dept Comp Sch Engn London England

ISBN: (数字)9781538685174

ISBN: (纸本)9781538685174

Human action recognition (HAR) has been widely employed in various applications such as autonomous cars and intelligent video surveillance. Among the algorithms proposed for HAR, the 3D-CNNs algorithm can achieve the best accuracy. However, its algorithmic complexity imposes a substantial overhead over the speed of these networks, which limits their deployment in real-life applications. this paper proposes a novel customizable architecture for 3D-CNNs based on block floating-point (BFP) arithmetic, where the utilization of BFP significantly reduces the bitwidth while eliminating the need to retrain the network. Optimizations such as locality exploration and block alignment with 3D blocking are performed to improve performance and accuracy. An analytical model and tool are developed to predict the optimized parameters for hardware customization based on user constraints such as FPGA resources or accuracy requirement. Experiments show that without retraining, a 15 bit mantissa design using single-precision accumulation on a Xilinx ZC706 device can be 8.2 times faster than an Intel i7-950 processor at 3.07 GHz with only 0.4% accuracy loss.

关键词： three-dimensional displays field programmable gate arrays Convolution Acceleration Two dimensional displays Optimization Hardware

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