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检索条件"任意字段=17th International Conference on Field Programmable Logic and Applications"

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Demonstration of Object Detection for Event-driven Cameras on FPGAs and GPUs 28

Demonstration of Object Detection for Event-driven Cameras o...

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28th international conference on field programmable logic and applications (FPL)

作者： Shimoda, Masayuki Sato, Shimpei Nakahara, Hiroki Tokyo Inst Technol Tokyo Japan

ISBN: (数字)9781538685174

ISBN: (纸本)9781538685174

We demonstrate an object detection system using a sliding window method for an event-driven camera[3] which outputs a subtracted frame (usually a binary value) when changes are detected in captured images. Fig. 1 shows the overall architecture of the object detector using a sliding window. First, our system extracts the object region candidates by applying a sliding window to the picture output by an event-driven camera. Since the event-driven camera outputs are binary, the sliding window determines whether an object exists or not based on the proportion of white pixels inside the bounding box as shown in Fig. 2. It reduces the number of proposed regions from 1,485 to average 10. the extracted pictures are resized to 40 x 40 size and applied to the ABCNN (All Binarized Convolutional Neural Network[7]), which is a BCNN (Binarized Convolutional Neural Network[4]) in which the first convolutional layer is done in binary form as well. All binarization is found to improve both the area and computation time, while the classification accuracy decreases. If the ABCNN infers the detected object as human, then it draws a box on the proposed region. Since more than one bounding box is commonly drawn against a single detected object, non-maximum suppression is used to reduce the extras to a single box. the proposed system is implemented on an FPGA and a GPU to show the comparison of them.

关键词： Cameras field programmable gate arrays Microsoft Windows Graphics processing units Micromechanical devices Neural networks Object detection

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Design Flow of Accelerating Hybrid Extremely Low Bit-width Neural Network in Embedded FPGA 28

Design Flow of Accelerating Hybrid Extremely Low Bit-width N...

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28th international conference on field programmable logic and applications (FPL)

作者： Wang, Junsong Lou, Qiuwen Zhang, Xiaofan Zhu, Chao Lin, Yonghua Chen, Deming IBM Res China Beijing Peoples R China Univ Notre Dame Notre Dame IN 46556 USA Univ Illinois Champaign IL USA

ISBN: (数字)9781538685174

ISBN: (纸本)9781538685174

Neural network accelerators with low latency and low energy consumption are desirable for edge computing. To create such accelerators, we propose a design flow for accelerating the extremely low bit-width neural network (ELB-NN) in embedded FPGAs with hybrid quantization schemes. this flow covers both network training and FPGA-based network deployment, which facilitates the design space exploration and simplifies the tradeoff between network accuracy and computation efficiency. Using this flow helps hardware designers to deliver a network accelerator in edge devices under strict resource and power constraints. We present the proposed flow by supporting hybrid ELB settings within a neural network. Results show that our design can deliver very high performance peaking at 103 TOPS and classify up to 325.3 image/s/watt while running large-scale neural networks for less than 5W using embedded FPGA. To the best of our knowledge, it is the most energy efficient solution in comparison to GPU or other FPGA implementations reported so far in the literature.

关键词： field programmable gate arrays Neural networks Quantization (signal) Training Hardware Tools Acceleration

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Embracing Diversity: Enhanced DSP Blocks for Low-Precision Deep Learning on FPGAs 28

Embracing Diversity: Enhanced DSP Blocks for Low-Precision D...

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28th international conference on field programmable logic and applications (FPL)

作者： Boutros, Andrew Yazdanshenas, Sadegh Betz, Vaughn Univ Toronto Dept Elect & Comp Engn Toronto ON Canada Vector Inst Toronto ON Canada

ISBN: (数字)9781538685174

ISBN: (纸本)9781538685174

Use of reduced precisions in Deep Learning (DL) inference tasks has recently been shown to significantly improve accelerator performance and greatly reduce both model memory footprint and the required external memory bandwidth. With appropriate network retuning, reduced precision networks can achieve accuracy close or equal to that of full-precision floating-point models. Given the wide spectrum of precisions used in DL inference, FPGAs' ability to create custom bit-width datapaths gives them an advantage over other acceleration platforms in this domain. However, the embedded DSP blocks in the latest Intel and Xilinx FPGAs do not natively support precisions below 18-bit and thus can not efficiently pack low-precision multiplications, leaving the DSP blocks under-utilized. In this work, we present an enhanced DSP block that can efficiently pack 2x as many 9-bit and 4x as many 4-bit multiplications compared to the baseline Arria-10-like DSP block at the cost of 12% block area overhead which leads to only 0.6% total FPGA core area increase. We quantify the performance gains of using this enhanced DSP block in two state-of-the-art convolutional neural network accelerators on three different models: AlexNet, VGG-16, and ResNet-50. On average, the new DSP block enhanced the computational performance of the 8-bit and 4-bit accelerators by 1.32x and 1.6 x and at the same time reduced the utilized chip area by 15% and 30% respectively.

关键词： field programmable gate arrays Compressors Memory management Degradation Computational modeling

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Towards in the field fast pathogens detection using FPGAs 28

Towards in the field fast pathogens detection using FPGAs

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28th international conference on field programmable logic and applications (FPL)

作者： Casale-Brunet, S. Schuepbach, T. Guex, N. Iseli, C. Bridge, A. Kuznetsov, D. Sigrist, C. Lemercier, P. Xenarios, I. Bezati, E. Swiss Inst Bioinformat Lausanne Switzerland

ISBN: (数字)9781538685174

ISBN: (纸本)9781538685174

the rapid detection and identification of infectious pathogens are a critical need for healthcare in both developed and developing countries. there is a need for portable diagnostics and epidemiological surveillance systems that can be deployed in remote field settings for infectious diseases testing, such as pandemic "hotspots" in Africa or southeast Asia. Together with the Vital-IT and Swiss-Prot groups, we developed a fast pathogen detection embedded hardware accelerator (no bigger than 75x50mm) capable of analyzing up to 250Mnt/s of DNA sequence. To deploy this solution, an embedded DNA Next Generation Sequencer (NGS) is used for retrieving the genetic material from patients sample at the point of care (e.g., the Oxford Nanopore Technologies MinION). Successively, the collected DNA sequences are analized in order to detect the presence of known pathogen patterns. Currently, up to 100 different pathogens can be analized at the same time using one single embedded accelerator. Due to the low-power consumption of this hardware accelerator, it is possible to give access to worldwide health organizations and local administrations to a complete real-time embedded and battery powered surveillance solution. Moreover, this solution can greatly scale to big computing clusters, where a larger pathogens number can be analized in parallel, outperforming current state of art computationally expensive solutions.

关键词： pathogens detection FPGA genomics

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Medusa: A Scalable Interconnect for Many-Port DNN Accelerators and Wide DRAM Controller Interfaces 28

Medusa: A Scalable Interconnect for Many-Port DNN Accelerato...

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28th international conference on field programmable logic and applications (FPL)

作者： Shen, Yongming Ji, Tianchu Ferdman, Michael Milder, Peter SUNY Stony Brook Stony Brook NY 11794 USA

ISBN: (数字)9781538685174

ISBN: (纸本)9781538685174

To cope with the increasing demand and computational intensity of deep neural networks (DNNs), industry and academia have turned to accelerator technologies. In particular, FPGAs have been shown to provide a good balance between performance and energy efficiency for accelerating DNNs. While significant research has focused on how to build efficient layer processors, the computational building blocks of DNN accelerators, relatively little attention has been paid to the on-chip interconnects that sit between the layer processors and the FPGA's DRAM controller. We observe a disparity between DNN accelerator interfaces, which tend to comprise many narrow ports, and FPGA DRAM controller interfaces, which tend to be wide buses. this mismatch causes traditional interconnects to consume significant FPGA resources. To address this problem, we designed Medusa: an optimized FPGA memory interconnect which transposes data in the interconnect fabric, tailoring the interconnect to the needs of DNN layer processors. Compared to a traditional FPGA interconnect, our design can reduce LUT and FF use by 4.7x and 6.0x, and improves frequency by 1.8x.

关键词： Random access memory Bandwidth Data transfer field programmable gate arrays Program processors Buffer storage Multiplexing

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FINN-L: Library Extensions and Design Trade-off Analysis for Variable Precision LSTM Networks on FPGAs 28

FINN-L: Library Extensions and Design Trade-off Analysis for...

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28th international conference on field programmable logic and applications (FPL)

作者： Rybalkin, Vladimir Ghaffar, Muhammad Mohsin Wehn, Norbert Pappalardo, Alessandro Gambardella, Giulio Blott, Michaela Univ Kaiserslautern Microelect Syst Design Res Grp Kaiserslautern Germany Xilinx Res Labs Dublin Ireland

ISBN: (数字)9781538685174

ISBN: (纸本)9781538685174

It is well known that many types of artificial neural networks, including recurrent networks, can achieve a high classification accuracy even with low-precision weights and activations. the reduction in precision generally yields much more efficient hardware implementations in regards to hardware cost, memory requirements, energy, and achievable throughput. In this paper, we present the first systematic exploration of this design space as a function of precision for Bidirectional Long Short-Term Memory (BiLSTM) neural network. Specifically, we include an in-depth investigation of precision vs. accuracy using a fully hardware-aware training flow, where during training quantization of all aspects of the network including weights, input, output and in-memory cell activations are taken into consideration. In addition, hardware resource cost, power consumption and throughput scalability are explored as a function of precision for FPGA-based implementations of BiLSTM, and multiple approaches of parallelizing the hardware. We provide the first open source HLS library extension of FINN [1] for parameterizable hardware architectures of LSTM layers on FPGAs which offers full precision flexibility and allows for parameterizable performance scaling offering different levels of parallelism within the architecture. Based on this library, we present an FPGA-based accelerator for BiLSTM neural network designed for optical character recognition, along with numerous other experimental proof points for a Zynq UltraScale+ XCZU7EV MPSoC within the given design space.

关键词： Computer architecture Hardware Quantization (signal) Training field programmable gate arrays Microprocessors Libraries

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Efficient Pattern Recognition Algorithm Including a Fast Retina Keypoint FPGA Implementation

Efficient Pattern Recognition Algorithm Including a Fast Ret...

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international conference on field programmable logic and applications

作者： Lester Kalms Maximilian Hajduk Diana Göhringer Technische Universität Dresden Dresden Germany

the field of computer vision is continuously increasing and becoming more complex and power demanding. Using feature detection and description allows a fast object detection without needing big databases. FPGAs are predestined for different requirements, like real-time and power constraints, which are important in many application areas. this work proposes a new pattern recognition algorithm, based on an improved Accelerated KAZE (AKAZE) detector and Fast Retina Keypoint (FREAK) descriptor. Our software implementation increased the repeatability in comparison to the original algorithm using optimized configurations. the percentage of correct matching features between two images (repeatability) increased from 85.7% to 91.4%, while the computation time decreases from 70.3ms to 24.9ms. Furthermore, we present an efficient FPGA implementation of the FREAK descriptor. the accelerator processes 2048 features at 73.4 frames per second; achieving a repeatability of 90.9%, while being optimized for resource utilization and memory bandwidth consumption. Additionally, we show an efficient Integral Image implementation that processes four image pixels per clock cycle at a high frequency (204 MHz on xc7z020clg484-1) consuming minimum resources.

关键词： field programmable gate arrays Retina Detectors Feature detection Pattern recognition Feature extraction Software algorithms

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Mitigating DDoS Flooding Attacks against IoT using Custom Hardware Modules 6

Mitigating DDoS Flooding Attacks against IoT using Custom Ha...

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6th international conference on Internet of things - Systems, Management and Security (IOTSMS)

作者： Brasilino, Lucas R. B. Swany, Martin Indiana Univ Sch Informat Comp & Engn 700 N Woodlawn Ave Bloomington IN 47408 USA

ISBN: (纸本)9781728129495

the increasing number of deployed Internet of things (IoT) devices is supporting a plethora of new applications that enriches our daily lives. Smart Cities, for instance, leverage IoT to enable new ways of interactions among citizens, government, public services, healthcare, natural resources, waste and energy management. this synergy pushes the participation of individuals and organizations to new levels, strengthening democracy. However, the ubiquity of such devices and their unique characteristics of being numerous, constantly connected to the Internet and having constrained processing capabilities turned IoT into the new target of cyberattacks. Lately, we have witnessed an alarming increase in attack events towards IoT. the most common pattern is usually done in two phases. In the first phase, attackers exploit vulnerabilities in as many devices as possible, turning them into their bots. In the second phase, attackers order bots to dispatch as many request as possible towards a chosen target, flooding them with requests, attempting to exhaust device's computing resources: a Distributed Denial of Service (DDoS) is in place. the traditional targets of massive DDoS attacks are eminent organizations, like financial institutions, governments and online retailers. However, there is space still for small scale DDoS attacks towards IoT devices itself. the main objective would be bringing down IoT devices which firmwares are not easily exploitable, such as security/video surveillance devices. In this paper, we present a study on DDoS flooding attack mitigation where IoT devices are the targets. To that end, we propose a feasible architecture leveraging a CoAP Accelerator to effectively improve device's resilience. the CoAP Accelerator works in cooperation with the device's CPU, having a key role on CoAP message processing. the architecture was prototyped in a System-on-Chip (SoC) field programmable Gate Array (FPGA) and evaluations were carried out demonstrating how devi

关键词： Internet of things IoT FPGA programmable logic Embedded Systems CoAP Security Resilience

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Performance Enhancement of Ge/GaAs Heterostructure Tunnelling field Effect Transistor

Performance Enhancement of Ge/GaAs Heterostructure Tunnellin...

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international conference on Nanomaterials: Application & Properties (NAP)

作者： Mohammed Farhan Jawad Tasnim Rahman Jibesh K. Saha Shahjalal University of Science and Technology Sylhet Bangladesh

ISBN: (数字)9781728185064

ISBN: (纸本)9781728185071

Tunnelling field Effect Transistor (TFET) is an emerging alternative to Metal Oxide Semiconductor field Effect Transistor (MOSFET) in device technology as the latter struggles with scaling down effects. But, low on-state current and abrupt doping profile are the limitations of TFET. However, Junctionless Tunnelling field Effect Transistor (JLTFET) has solved this doping problem by uniformly doping all the regions. A higher tunneling barrier causes the low on-state current, and that is still a limitation of the JLTFET. Our study aims to reduce the tunneling barrier to have a higher on-sate current using Ge/GaAs Heterostructure Junctionless Tunnelling field Effect Transistor (H-JLTFET) and enhance the overall performance of this H-JLTFET by analyzing different device parameters, such as channel thickness, oxide thickness, and doping concentration. the Non-Local Band to Band Tunnelling (BTBT) model was employed to achieve a realistic tunneling mechanism in our device using TCAD. Our proposed device provides a high on-state current of 7.68e-5 A/um, a low off-state current of 7.4e-17 A/um, nearly an ideal subthreshold swing of 5.73 mV/decade. Finally, this work concludes with a comparative study between our optimized device and other published similar TFET. the analysis shows that our device provides a significant improvement in performance, which could be very promising for the emerging low-power, high-speed VLSI technology.

关键词： Tunneling Doping Performance evaluation logic gates Capacitance TFETs threshold voltage

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AConFPGA: A Multiple-Output Boolean Function Approximation DSE Technique Targeting FPGAs 17

AConFPGA: A Multiple-Output Boolean Function Approximation D...

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17th international conference on field-programmable Technology (FPT)

作者： Echavarria, Jorge Wildermann, Stefan Teich, Juergen Friedrich Alexander Univ Erlangen Nurnberg FAU Dept Comp Sci D-91058 Erlangen Germany

ISBN: (纸本)9781728102139

New relaxed quality standards laid down by approximate computing enrich the design pool with architectures dissipating less power, consuming fewer resources or with smaller latencies. In LUT-based FPGA logic approximation, the number of LUTs and latency associated to a design can be optimized by allowing the approximation of circuit results. In this paper, we present techniques for automatic design space exploration (DSE) of Boolean function falsifications and the ability and impact to reduce resources usage as well as the length of critical paths on LUT-based FPGAs. Our experiments give evidence that resource reductions of about 20% are easily achievable for error rates amounting to less than 0.05% w.r.t. accurate designs.

关键词： Approximate Computing logic Simplification Design Space Exploration FPGAs

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