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检索条件"任意字段=17th International Conference on Field Programmable Logic and Applications"

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AConFPGA: A Multiple-Output Boolean Function Approximation DSE Technique Targeting FPGAs 17

AConFPGA: A Multiple-Output Boolean Function Approximation D...

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17th international conference on field-programmable Technology (FPT)

作者： Echavarria, Jorge Wildermann, Stefan Teich, Juergen Friedrich Alexander Univ Erlangen Nurnberg FAU Dept Comp Sci D-91058 Erlangen Germany

ISBN: (纸本)9781728102139

New relaxed quality standards laid down by approximate computing enrich the design pool with architectures dissipating less power, consuming fewer resources or with smaller latencies. In LUT-based FPGA logic approximation, the number of LUTs and latency associated to a design can be optimized by allowing the approximation of circuit results. In this paper, we present techniques for automatic design space exploration (DSE) of Boolean function falsifications and the ability and impact to reduce resources usage as well as the length of critical paths on LUT-based FPGAs. Our experiments give evidence that resource reductions of about 20% are easily achievable for error rates amounting to less than 0.05% w.r.t. accurate designs.

关键词： Approximate Computing logic Simplification Design Space Exploration FPGAs

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FPGA Implementation of an Improved Watchdog Timer for Safety-critical applications 31

FPGA Implementation of an Improved Watchdog Timer for Safety...

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31st international conference on VLSI Design / 17th international conference on Embedded Systems (VLSID & ES))

作者： Unni, Ravi Krishnan Vijayanand, P. Dilip, Y. Def Res & Dev Org Aeronaut Dev Estab Bangalore 560075 Karnataka India

ISBN: (纸本)9781538636923

Embedded systems that are employed in safety-critical applications require highest reliability. External watchdog timers are used in such systems to automatically handle and recover from operation time related failures. Most of the available external watchdog timers use additional circuitry to adjust their timeout periods and provide only limited features in terms of their functionality. this paper describes the architecture and design of an improved configurable watchdog timer that can be employed in safety-critical applications. Several fault detection mechanisms are built into the watchdog, which adds to its robustness. the functionality and operations are rather general and it can be used to monitor the operations of any processor based real-time system. this paper also discusses the implementation of the proposed watchdog timer in a field programmable Gate Array (FPGA). this allows the design to be easily adaptable to different applications, while reducing the overall system cost. the effectiveness of the proposed watchdog timer to detect and respond to faults is first studied by analysing the simulation results. the design is validated in a real-time hardware by injecting faults through the software while the processor is executing, and conclusions are drawn.

关键词： Real time systems

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FPGA-Based Simulated Bifurcation Machine

FPGA-Based Simulated Bifurcation Machine

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international conference on field programmable logic and applications

作者： Kosuke Tatsumura Alexander R. Dixon Hayato Goto Toshiba Corporation

Since many combinatorial optimization problems can be mapped onto ground-state search problems of Ising models, special-purpose machines for Ising problems have attracted intense attention. Simulated bifurcation (SB) is a recently proposed algorithm to solve these Ising problems. One of the remarkable features of SB is the high-degree parallelism underlying in the algorithm, providing an opportunity to solve the Ising problems very fast by massively parallel processing. In this work, we implement the SB algorithm on FPGAs by designing massively parallel custom circuits. We then compare the FPGA-based SB machines with a state-of-the-art machine called a coherent Ising machine (CIM), a highly optimized implementation of simulated annealing (SA), and GPU-based SB machines. SB machines with spin size of 2,048/4,096 (2K/4K) on an Arria10 GX1150 FPGA have 8,192 processing elements for the matrix-vector multiplication (MM) modules (the most computationally intensive part) and achieve computation throughput of 1,873/2,027 GMAC/s for the MM modules, outperforming 2K/4K SB machines on an Nvidia Tesla V100 GPU (113/183 GMAC/s). the 2K FPGA-SB solves all-to-all connected 2000-node MAX-CUT problem 14X (/124X) faster than the CIM (/the highly-optimized SA), with much better energy efficiency (288X better than the CIM).

关键词： Oscillators Bifurcation Parallel processing field programmable gate arrays Optimization Graphics processing units Computational complexity

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In-Package Domain-Specific ASICs for Intel® Stratix® 10 FPGAs: A Case Study of Accelerating Deep Learning Using TensorTile ASIC 28

In-Package Domain-Specific ASICs for Intel® Stratix® 10 FP...

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28th international conference on field programmable logic and applications (FPL)

作者： Nurvitadhi, Eriko Cook, Jeffrey J. Mishra, Asit Marr, Debbie Nealis, Kevin Colangelo, Philip Ling, Andrew Capalija, Davor Aydonat, Utku Dasu, Aravind Shumarayev, Sergey Intel Corp Santa Clara CA 95051 USA

ISBN: (数字)9781538685174

ISBN: (纸本)9781538685174

FPGAs or ASICs? FPGAs are extremely flexible while ASICs offer top efficiency. We believe that FPGAs and ASICs are better together, to offer flexibility and efficiency. We propose single-package heterogeneous 2.5D integration of FPGAs and ASICs, using Intel's Embedded Multi-Die Interconnect Bridge (EMIB). Since the ASICs are separate chips from the FPGA, this approach (1) does not change FPGA fabric, allowing re-use of existing ecosystems (FPGA chips, packaging, boards, software), and (2) allows freedom in ASIC design (area/freq/process/etc unconstrained by FPGA fabric). Intel (R) Stratix (R) 10 FPGAs already have EMIBs, enabling single-package integration with other chips, or "tiles". We propose leveraging them to mix-and match any domain-specific ASICs with Stratixl0 FPGAs. In particular, this work focuses on deep learning (DL) domain, which demands efficient tensor (matrix/vector) operations. We propose TensorTile ASICs for Stratixl0 FPGAs to provide ASIC-level tensor performance, while relying on FPGA's flexibility for application-specific operations (e.g., Winograd). Our evaluation shows: (1) a small TensorTile offer much better tensor throughput than a large Stratixl02800 FPGA;(2) FPGAs and TensorTiles mix-and-match provide scalable solutions (e.g., similar to 69 peak INT8 TOPs with 1xTensorTile+sm all Stratixl0-400 FPGA, to 194 peak FP16 TOPs with 6xTensorTiles+large Stratixl0-2800);(3) AlexNet performance (performance/Watt) of Intel's DL FPGA design improved by 4x (3.3x) when enhanced with 2xTensorTiles.

关键词： field programmable gate arrays Tensile stress Fabrics Computer architecture Parallel processing Acceleration

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Proceedings - 2018 international conference on field-programmable Technology, FPT 2018

Proceedings - 2018 International Conference on Field-Program...

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17th international conference on field-programmable Technology, FPT 2018

ISBN: (纸本)9781728102139

the proceedings contain 81 papers. Topics discussed include: accelerating top-k listnet training for ranking using FPGA;novel neural network applications on new python enabled platforms;tatum: parallel timing analysis for faster design cycles and improved optimization;DP-pack: distributed parallel packing for FPGAs;leflow: automatic compilation of tensorflow machine learning applications to FPGAs;FPGA acceleration of a supervised learning method for hyperspectral image classification;a study on introducing FPGA to ROS based autonomous driving system;real-time object detection and semantic segmentation hardware system with deep learning networks;and dither NN: an accurate neural network with dithering for low bit-precision hardware.

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LeFlow: Automatic Compilation of TensorFlow Machine Learning applications to FPGAs 17

LeFlow: Automatic Compilation of TensorFlow Machine Learning...

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17th international conference on field-programmable Technology (FPT)

作者： Noronha, Daniel Holanda Gibson, Kahlan Salehpour, Bahar Wilton, Steven J. E. Univ British Columbia Dept Elect & Comp Engn Vancouver BC Canada

ISBN: (纸本)9781728102139

Acceleration of Machine Learning applications on field-programmable Gate Arrays (FPGAs) has shown to have advantages over other computing platforms in recent work. However, since machine learning code is often specified in a high-level software language such as Python, the manual translation of the algorithm to either C code for high-level synthesis or to Register Transfer Level (RTL) code for synthesis is time consuming and requires the designer to have expertise in designing hardware. In order to show how we can make FPGAs more accessible to software developers, we present a demonstration of LeFlow: an open-source tool which maps numerical computation models written in TensorFlow to synthesizable RTL. this demonstration includes two examples which begin with a model written in TensorFlow and show how a designer would use the LeFlow tool to generate Verilog, simulate the result, and synthesize the design to target FPGAs.

关键词： Deep learning High level synthesis Machine learning Reconfigurable architectures Software tools

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Analytical Placement with 3D Poisson's Equation and ADMM Based Optimization for Large-Scale 2.5D Heterogeneous FPGAs 38

Analytical Placement with 3D Poisson's Equation and ADMM Bas...

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38th IEEE/ACM international conference on Computer-Aided Design (ICCAD)

作者： Chen, Jianli Zhu, Wenxing Yu, Jun He, Lei Chang, Yao-Wen Fudan Univ State Key Lab ASIC & Syst Shanghai Peoples R China Fuzhou Univ Ctr Discrete Math & Theoret Comp Sci Fuzhou Peoples R China Univ Calif Los Angeles Dept Elect Engn Los Angeles CA 90024 USA Natl Taiwan Univ Grad Inst Elect Engn Taipei 10617 Taiwan Natl Taiwan Univ Dept Elect Engn Taipei 10617 Taiwan

ISBN: (纸本)9781728123509

As the design complexity keep increasing, the 2.5D FPGA with large logic capacity has become popular in modern circuit applications. A 2.5D FPGA consists of multiple dies connected through super long lines (SLLs) on an interposer, where each die contains heterogeneous logic blocks and ASIC-like clocking architectures to achieve better skew and timing. To address the crucial SLL issue and the special clocking architecture, this paper presents the first analytical placement algorithm for the 2.5D FPGA with the objective of minimizing the numbers of inter-die SLL signals and intra-die clocking violations simultaneously. Using a lifting dimension technique, we first formulate the 2.5D global placement problem as a three-dimensional continuous and differential minimization problem, where the SLL-aware block distribution is modeled by 3D Poisson's equation and directly solved to obtain an analytical solution. then, we further reformulate the minimization problem as a separable optimization problem with linear constraints. Based on the proximal alternating direction method of multipliers (ADMM) optimization method, we efficiently optimize the separable subproblems one by one in an alternating fashion. Finally, clock-aware legalization and detailed placement are applied to legalize and further improve our placement results. Compared with the state-of-the-art work, experimental results show that our algorithm can resolve all clocking constraints and reduce the number of SLL crossing signals by 36.9% with similar wirelength in comparable running time.

关键词： field programmable gate arrays (FPGA)

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Designing Actively Secure, Highly Available Industrial Automation applications

Designing Actively Secure, Highly Available Industrial Autom...

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IEEE international conference on Industrial Informatics (INDIN)

作者： Awais Tanveer Roopak Sinha Stephen G. MacDonell Paulo Leitao Valeriy Vyatkin IT & Software Engineering Auckland University of Technology Auckland New Zealand Research Centre in Digitalisation and Intelligent Robotics (CeDRI) Instituto Politecnico de Braganca Braganca Portugal Aalto University Helsinki Finland

programmable logic Controllers (PLCs) execute critical control software that drives Industrial Automation and Control Systems (IACS). PLCs can become easy targets for cyber-adversaries as they are resource-constrained and are usually built using legacy, less-capable security measures. Security attacks can significantly affect system availability, which is an essential requirement for IACS. We propose a method to make PLC applications more security-aware. Based on the well-known IEC 61499 function blocks standard for developing IACS software, our method allows designers to annotate critical parts of an application during design time. On deployment, these parts of the application are automatically secured using appropriate security mechanisms to detect and prevent attacks. We present a summary of availability attacks on distributed IACS applications that can be mitigated by our proposed method. Security mechanisms are achieved using IEC 61499 Service-Interface Function Blocks (SIFBs) embedding Intrusion Detection and Prevention System (IDPS), added to the application at compile time. this method is more amenable to providing active security protection from attacks on previously unknown (zero-day) vulnerabilities. We test our solution on an IEC 61499 application executing on Wago PFC200 PLCs. Experiments show that we can successfully log and prevent attacks at the application level as well as help the application to gracefully degrade into safe mode, subsequently improving availability.

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Transparent Acceleration of Image Processing Kernels on FPGA-Attached Hybrid Memory Cube Computers 17

Transparent Acceleration of Image Processing Kernels on FPGA...

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17th international conference on field-programmable Technology (FPT)

作者： Pantho, Md Jubaer Hossain Mbongue, Joel Mandebi Bobda, Christophe Andrews, David Univ Arkansas Fayetteville AR 72701 USA

ISBN: (纸本)9781728102139

the Hybrid Memory Cube (HMC) is representative of emerging architectures that integrate FPGAs with multichannel interconnected 3-D stacked memory, offering great potential for high bandwidth streaming applications. However, creating new hardware components that tap the full potential of the concurrent communications channels requires the structural understanding of the memory layout and interconnect configurations. In this paper, we present a new development framework aimed at removing the need for software programmers to understand the underlying physical architecture. the proposed framework automates the creation of hardware/software co-designs for computer vision applications in a transparent way to the developer. the development system dynamically detects function calls in software kernels and replaces those calls by a hardware wrapper function that exploits the HMCs memory hierarchy and multichannel interconnect with the FPGA. Results show our flow can exploit the 3-D stacked memory and concurrent communications channels to achieve speed-up with no need to tune the original software application to the memory hierarchy.

关键词： field programmable Gate Arrays (FPGAs) Hybrid Memory Cube (HMC) OpenCV Heterogenous Systems

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TileNET: Scalable Architecture for High-throughput Ternary Convolution Neural Networks using FPGAs 31

TileNET: Scalable Architecture for High-throughput Ternary C...

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31st international conference on VLSI Design / 17th international conference on Embedded Systems (VLSID & ES))

作者： Vikram, Sahu Sai Pant, Vibha Mody, Mihir Purnaprajna, Madhura Amrita Univ Dept Elect & Commun Engn Bengaluru India Amrita Univ Dept Comp Sci Engn Bengaluru India Texas Instruments Inc Bengaluru India

ISBN: (纸本)9781538636923

Convolution Neural Networks (CNNs) are becoming increasing popular in Advanced driver assistance systems (ADAS) and Autonomated driving (AD) for camera perception enabling multiple applications like object detection, lane detection and semantic segmentation. Ever increasing need for high resolution multiple cameras around car necessitates a huge-throughput in the order of about few 10's of TeraMACs per second (TMACS) along with high accuracy of detection. Existing implementations do not scale, with performance ranging only in the order of a few Giga operations per second. this paper, proposes a novel tiled architecture for CNNs that uses only ternarized weights, while input and output features are kept full precision resulting in minimal loss of accuracy. the proposed solution is implemented on Virtex-7 FPGA resulting in throughput of 13.76 TOPS. the post-implementation power simulation for AlexNet consumes 16 W, orders of magnitude lower than exist in GPUs.

关键词： Convolution Acceleration field programmable gate arrays throughput Computer architecture Neural networks Electronic mail

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