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26th international conference on field-programmable logic and applications, FPL 2016

ISBN: (纸本)9782839918442

the proceedings contain 98 papers. the topics discussed include: high-speed PCAP configuration scrubbing on Zynq-7000 all programmable SoCs;boosting convergence of timing closure using feature selection in a learning-driven approach;liquid: fast placement prototyping through steepest gradient descent movement;TeSHoP : a temperature sensing based hotspot-driven placement technique for FPGAs;search-based synthesis of approximate circuits implemented into FPGAs;fast hierarchical NPN classification;and hardware acceleration of feature detection and description algorithms on low-power embedded platforms.

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A Review of Different Methods of Phase Measurement and its Suitable applications

A Review of Different Methods of Phase Measurement and its S...

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international conference for Convergence of Technology (I2CT)

作者： Marim Alan Phillimon Salam Devayani Devi Loitongbam Surajkumar Singh Department of ECE NIT Manipur Langol Imphal India

ISBN: (数字)9781538680759

ISBN: (纸本)9781538680766

the phase measurement technique using field programmable Gate Arrays (FPGAs) is a considerable improvement over previously available methods. It involves designing of simple suitable logic core, employing an improved method for sampling, simple design with less hardware and also with the introduction of the XOR-based phase detector to minimize jitter, thus achieving high accuracy and resolution and operate over a large range of frequency which is supported by the FPGA fabric. However, it is important to consider that there are different FPGAs based phase measurement techniques and are used in different applications considering each methods suits better in particular specific application. this paper presents a brief review of various methods for phase measurement, based on FPGA board, using various concepts and techniques in varied fields of science and technology.

关键词： Phase measurement field programmable gate arrays Clocks Frequency measurement Biomedical measurement Detectors Satellites

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Everyone's a critic: A tool for exploring RISC-V projects 28

Everyone's a critic: A tool for exploring RISC-V projects

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28th international conference on field-programmable logic and applications, FPL 2018

作者： Richmond, Dustin Barrow, Michael Kastner, Ryan Department of Computer Science and Engineering University of California San DiegoCA92195 United States

ISBN: (数字)9781538685174

ISBN: (纸本)9781538685174

the RISC-V specification is a highly flexible specification for low-cost processors. the RISC-V ISA is royalty free, vendor agnostic, easily portable between development environments, and highly flexible to match the demands of an application. these characteristics make RISC-V a natural ISA choice for an FPGA soft processor and this has led to widespread adoption in academia and industry. However, the sheer number of RISC-V projects can be daunting for potential users. this paper describes a tool for exploring RISC-V projects. Our tool provides a web-interface for executing C/C++ code, tests, and benchmarks. Our tool is packaged with interactive tutorials for extending, modifying, and reproducing our work. © 2018 IEEE.

关键词： field programmable gate arrays (FPGA)

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A Portable Image Processing Accelerator using FPGA 7

A Portable Image Processing Accelerator using FPGA

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7th international conference on Modern Circuits and Systems Technologies (MOCAST)

作者： Tsiktsiris, Dimitris Ziouzios, Dimitris Dasygenis, Minas Univ Western Macedonia Dept Informat & Telecommun Engn Kozani 50100 Greece

ISBN: (纸本)9781538647882

One of the most common uses of FPGAs is as implementation platforms for graphics processing applications. their structure can exploit spatial and temporal parallelism, but such parallelisation depends on the processing model and hardware constraints of the system. those restrictions can force the designer to reformulate the algorithm. In this paper we present an FPGA design as a portable USB accelerator device which implements the Grayscale and Sobel Edge Detection algorithms, two of the most fundamental algorithms in digital image processing.

关键词： Acceleration Image processing field programmable gate arrays programmable logic arrays Application software

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A Survey on FPGA Implementations in Embedded Augmented Reality applications 6

A Survey on FPGA Implementations in Embedded Augmented Reali...

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6th international conference on Wireless Networks and Embedded Systems (WECON)

作者： Kaur, Amanpreet Chitkara Univ Inst Engn & Technol Rajpura Punjab India

ISBN: (纸本)9781538670507

Since a long ago, most of the Augmented Reality (AR) applications are built using some general purpose devices such as computers and handhelds. In such general purpose devices, tasks are being processed using different softwares that make it difficult to obtain the real time results with high resolution and frame rate. there is a need to maintain a good performance but it invariably results into high cost of the overall project due to the requirement of higher clock frequency and high power. Mobility and processing power are the two basic requirements of an augmented reality application to provide an efficient immersion to the end user. An embedded architecture developed on field programmable Gate Array logic (FPGA) can supply both mobility and processing power to the AR applications. FPGA is a tiny chip that has the efficiency of hardware level executions. this paper gives a detailed account of FPGAs in AR applications in the field of computer vision & image processing, multimedia & computer graphics, communication and wearable computing.

关键词： FPGA augmented reality embedded systems reconfigurable hardware parallelism

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Realization of fractional order differintegral on the digital platform using FPGA and its time and frequency domain analysis

Realization of fractional order differintegral on the digita...

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international conference on Computing and Networking Technology (ICCNT)

作者： Ruchi Jain Centre for Research in Applied Electronics Indian Institute of Technology New Delhi India

this paper mainly focuses on the realization of the fractional operator on the digital platform. Discretization plays a key step for the practical realization of the fractional operator on hardware. Among the various available techniques of discretization, we have chosen a direct method of discretization using the Tustin operator and combined with the continued fraction expansion to get more effective discretized transfer function and realized the same on FPGA processor. Nowadays, in the domain of real-time applications in the digital world, FPGA emanated as the best alternative with the ability to perform multiple tasks simultaneously, highly flexible and reliable with simple design cycle, lower complexity, effective product cost, field reprogrammability, reusability, and reliability. In this paper, the designed module of the fractional operator in the form of fractional integrator and differentiator of order 0.5 is implemented on programmable logic design software Quartus II and verified on DEO Nano Board (Cyclone IV FPGA family of company Altera). the performance of hardware realized module is analyzed in frequency and time domain, and results are examined with its MATLAB counterpart.

关键词： field programmable gate arrays Hardware Frequency-domain analysis Software Poles and zeros Real-time systems

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1st international conference on 'Mechatronics and Artificial Intelligence' (ICMAI-2021)

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Journal of Physics: conference Series 2021年第1期1950卷

PREFACE It was a matter of pleasure to organize 1st international conference on 'Mechatronics and Artificial Intelligence' (ICMAI-2021) at Shree Guru Gobind Singh Tricentenary (SGT) University, Gurugram on 26th and 27th February 2021. the conference was organized in Association of Engineering & Technocrats, Faculty of Engineering and Technology, SGT University. the objective of this conference was to provide a common platform to scientists and researchers from all over India for exchanging their knowledge and views to deal with global challenges. the theme of this conference was not only the fundamental technology in the field of engineering science but also can change our society by exploring new horizons and continuous progress. A diverse range of topics from the neural network, digital image processing, machine learning, programmable logic controller, health care, IoT based systems, deep learning, lean manufacturing, abrasive flow machining, welding technology and simulation-based studies are featured in the conference. In addition to that, you will also hear about the incremental forming, automation integration techniques, wireless sensor techniques, non-invasive methods of diagnosis, robot assembly, data mining and various evolutionary algorithms in different applications. I hope, therefore, that you will get a chance to explore recent emerging technologies. We are delighted to deliver special thanks to IOP Publishing as our publication partner to publish the conference proceedings in JPCS. We sincerely thanks to our sponsors Council of Scientific and Industrial Research (CSIR) Human Resource Development Group (HRDG) and 'Sanranchana', SGT University Center of Research Innovation. We believe that the conference had provided the opportunity to the students and the young researchers for enriching their knowledge through interaction with eminent researchers from various NITs, IITs, state universities and reputed organizations. We hope that everybody had a great ex

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An FPGA implementation of a time-to-digital converter with a ring oscillator and buffers 17

An FPGA implementation of a time-to-digital converter with a...

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17th international conference on Electronics, Information and Communication, ICEIC 2018

作者： Van Luan, Dinh Truong, Nguyen Xuan Lee, Hyuk-Jae Seoul National University Korea Republic of

ISBN: (纸本)9781538647547

A Time-to-Digital Converter (TDC) is widely used in applications that need to measure the time interval between events. Previous designs based on a feedback loop and an extended delay line suffer from poor accuracy caused by the non-linearity of a delay line. To overcome the poor accuracy in the previous TDC, this paper proposes a novel TDC that uses a ring oscillator to measure the interval by counting the number of cycles in the interval. To reduce the precision drop by the measurement with the ring oscillator, an additional delay line is used in the TDC. the proposed TDC is implemented by using Xilinx Spartan-6 LX9 FPGA with 20MHz oscillator. © 2018 Institute of Electronics and Information Engineers.

关键词： field programmable gate arrays (FPGA)

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FASE: FPGA Acceleration of Secure Function Evaluation

FASE: FPGA Acceleration of Secure Function Evaluation

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Annual IEEE Symposium on field-programmable Custom Computing Machines (FCCM)

作者： Siam U. Hussain Farinaz Koushanfar University of California San Diego

We present FASE, an FPGA accelerator for Secure Function Evaluation (SFE) by employing the well-known cryptographic protocol named Yao's Garbled Circuit (GC). SFE allows two parties to jointly compute a function on their private data and learn the output without revealing their inputs to each other. FASE is designed to allow cloud servers to provide secure services to a large number of clients in parallel while preserving the privacy of the data from both sides. Current SFE accelerators either target specific applications, and therefore are not amenable to generic use, or have low throughput due to inefficient management of resources. In this work, we present a pipelined architecture along with an efficient scheduling scheme to ensure optimal usage of the available resources. the scheme is built around a simulator of the hardware design that schedules the workload and assigns the most suitable task to the encryption cores at each cycle. this, coupled with optimal management of the read and write cycles of the Block RAM on FPGA, results in a minimum 2 orders of magnitude improvement in terms of throughput per core for the reported benchmarks compared to the most recent generic GC accelerator. Moreover, our encryption core requires 17% less resource compared to the most recent secure GC realization.

关键词： logic gates field programmable gate arrays Encryption Protocols Servers Acceleration Wires

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QoS-aware Cross-layer Reliability-integrated FPGA-based Dynamic Partially Reconfigurable System Partitioning 17

QoS-aware Cross-layer Reliability-integrated FPGA-based Dyna...

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17th international conference on field-programmable Technology (FPT)

作者： Sahoo, Siva Satyendra Nguyen, Tuan D. A. Veeravalli, Bharadwaj Kumar, Akash Natl Univ Singapore Dept ECE Singapore Singapore Tech Univ Dresden Ctr Adv Elect Dresden Dresden Germany

ISBN: (纸本)9781728102139

Dynamic Partial Reconfiguration (DPR) can be used for time-sharing of computing resources within Partially Reconfigurable Regions (PRRs) in FPGA-based systems. the heterogeneous partitioning in such systems allows the user to exploit the application-specific mapping of Partially Reconfigurable Modules (PRMs) to PRRs to implement more efficient designs. It offers increased opportunities in optimizing the reliability of the system across multiple layers from the low-level physical one to the higher application layer. this method, called cross-layer reliability, can potentially exploit the application-specific tolerances to the quality of service (QoS) to tackle the increasing device fault-rates more cost-effectively by distributing the faultmitigation to different layers. In this work, we propose a QoSaware cross-layer reliability-integrated design methodology for FPGA-based DPR systems. Specifically, our methodology analyzes the requirements of the applications in terms of Functional Reliability, System Lifetime and Makespan to determine the best possible combinations of reliability-oriented design choices in different layers. We report up to an average of 24% and 30% performance improvements for single and multi-objective optimization-based system partitioning.

关键词： Cross-layer Reliability Dynamic Partial Reconfiguration field programmable Gate Arrays Embedded Systems

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