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Accuracy Improvement for Neural Program Synthesis via Attention Mechanism and Program Slicing

Accuracy Improvement for Neural Program Synthesis via Attent...

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IEEE Annual international Computer Software and applications conference (COMPSAC)

作者： Yating Zhang Wei Dong Daiyan Wang Binbin Liu Jiaxin Liu National University of Defense Technology

ISBN: (数字)9781728173030

ISBN: (纸本)9781728173047

Program synthesis, the task of automatically finding programs from the underlying programming language that satisfy user intent expressed in some form of constraints, has been regarded as one of the most central problems and hottest research fields in the theory of programming. On the other hand, the development of neural networks and deep learning in many fields has led researchers to consider the possibility of applying them to solve the program synthesis problems. In this paper, we took the probabilistic program synthesis realized by the neural network as the research subject and noticed that most of the current work borrows from the structure of encoding and decoding in natural language processing. We analyzed its two possible disadvantages, one is the performance degradation of the long-sequence structure, the other is that synthesized results without validation are too redundant. We took a probabilistic encoder-decoder neural model named BAYOU as an example to analyze the specific problem. We proposed a framework named PASS which contains several methods to solve those problems and improve the model performance. For the former problem, we showed how to adapt neural networks to increase the attention mechanism to address the problem of information forgetting and long sequences unmanageable. then, we combined the program slicing in the field of program analysis to slice the generated program, thereby eliminated redundant code of result from methods without validation and had a more refined result. the experiment showed that the accuracy of neural program synthesis guided from our approach improved by a mean of 17%, up to a maximum of 22%. Besides, the slicing work of our approach succeeded in a mean about code refinement rate of 25.3% for those methods without result validation.

关键词： Decoding Neural networks Probabilistic logic Task analysis Programming Search problems Machine learning

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SMEM++: A pipelined and time-multiplexed SMEM seeding accelerator for genome sequencing 28

SMEM++: A pipelined and time-multiplexed SMEM seeding accele...

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28th international conference on field-programmable logic and applications, FPL 2018

作者： Cong, Jason Guo, Licheng Huang, Po-Tsang Wei, Peng Yu, Tianhe University of California Los Angeles United States National Chiao Tung University Taiwan

ISBN: (数字)9781538685174

ISBN: (纸本)9781538685174

Next-generation sequencing motivates the researchof FPGA acceleration for genome sequencing algorithms. therecently developed quadratic-time SMEM seeding algorithmbecomes a time-consuming computation kernel in genomesequencing, but it has not been well studied. the fundamentalchallenge of accelerating the SMEM algorithm is to handle itslarge volume of random memory accesses. While the state-ofthe-art SMEM accelerator attempts sacrifices the performanceof individual processing elements to maximize the task-levelparallelism, this methodology suffers a serious resource underutilizationissue. therefore, we propose SMEM++, a pipelinedand time-multiplexed FPGA accelerator for SMEM ***++ adopts the canonical non-blocking pipelinemethodology and implements a fully pipelined acceleratorwith initiation interval equal to one. Moreover, we designa communication interface adapter to make the acceleratorcompatible to the target platform interface and increase itsportability. Experiments on the Intel HARPv2 platform showthat SMEM++ outperforms the original software by 24x, andoutperforms the state-of-the-art SMEM accelerator design by6.3x, with 43% less logic resource usage. © 2018 IEEE.

关键词： field programmable gate arrays (FPGA)

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CAD Tool Flow for Variation-Tolerant Non-Volatile STT-MRAM LUT based FPGA 2018

CAD Tool Flow for Variation-Tolerant Non-Volatile STT-MRAM L...

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7th international conference on Software and Computer applications (ICSCA)

作者： Kim, Jeongbin Kim, Ki Tae Chung, Eui-Young Yonsei Univ Dept Elect & Elect Engn Seoul South Korea

ISBN: (纸本)9781450354141

field programmable Gate Array (FPGA) is a reconfigurable circuit and it is used for various applications such as image processing, digital signal processing and neural network. FPGA adopts a logic circuit called Look-Up Table (LUT) as a basic circuit structure. Commonly used FPGAs have volatile characteristic because it consists of SRAM based LUT that adopts SRAM as a memory cell. Volatile FPGAs have a disadvantage in terms of power management efficiency. Variation-Tolerant Non-Volatile STT-MRAM (VTNV) LUT has been studied for a nonvolatile FPGAs and it has unique characteristics that can only operate in the half clock period. Accordingly, VTNV LUT based FPGA cannot operate normally with conventional FPGA CAD tool flow. We propose FPGA CAD (Computer Aided Design) tool flow for VTNV LUT based FPGA with supporting unique characteristic of VTNV LUT, and implement a non-volatile FPGA. through proposed FPGA CAD tool flow, non-volatile FPGA based on VTNV LUT could operate normally. Because of high parameters of VTNV LUT, experimental results show that power increases by 29% and critical path delay increases by 16%, but it'll be improved sufficiently by future VTNV LUT researches.

关键词： Computer aided design (CAD) field programmable gate array (FPGA) CAD tool flow non-volatile FPGA

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Hot & Spicy: Improving Productivity with Python and HLS for FPGAs 26

Hot & Spicy: Improving Productivity with Python and HLS for ...

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26th IEEE Annual international Symposium on field-programmable Custom Computing Machines (FCCM)

作者： Skalicky, Sam Monson, Joshua Schmidt, Andrew French, Matthew Univ Southern Calif Informat Sci Inst Arlington VA 91802 USA

ISBN: (纸本)9781538655221

We present Hot & Spicy an open-source infrastructure and tool suite for integrating FPGA accelerators in Python applications, provided entirely as Python source code and available at https: //spicy. isi .edu . this suite of tools eases the packaging, integration, and binding of accelerators and their C/C++ based drivers callable from a Python application. the Hot & Spicy tools can: (1) translate Python functions to HLS-suitable C functions, (2) generate Python C wrapper bindings, (3) automate the FPGA EDA tool flow, and (4) retarget Python source code to use accelerated libraries. For FPGA experts, this enables increased productivity and supports research on each stage of the flow by providing a framework to integrate additional compilers and optimizations. For everyone else this enables fast, consistent, acceleration of applications on FPGAs. We describe the design principles and flows for supporting high-level Python abstractions in an FPGA development flow. then we evaluate the overheads of calling C/C++ routines from Python. Lastly, we show the results of accelerating a kernel in a Python image processing application and achieve a 39,137x speedup over the original Python implementation, and 6x speedup over an high-performance, hand-optimized OpenCV library implementation.

关键词： Tools Python field programmable gate arrays Acceleration Hardware design languages Syntactics Hardware"

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AutoRARE: An Automated Tool For Generating FPGA-Based Multi-Memory Hardware Accelerators For Compute-Intensive applications 37

AutoRARE: An Automated Tool For Generating FPGA-Based Multi-...

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37th IEEE international Performance Computing and Communications conference (IPCCC)

作者： Jadhav, Shrikant S. Gloster, Clay Doss, Christopher Kim, Youngsoo Naher, Jannatun North Carolina A&T State Univ Dept Elect & Comp Engn Greensboro NC 27401 USA North Carolina A&T State Univ Dept Comp Syst Technol Greensboro NC USA Bradley Univ Dept Elect & Comp Engn Peoria IL 61625 USA

ISBN: (纸本)9781538668085

In this paper, we present AutoRARE, a Java-based automated design tool for generating field programmable Gate Array (FPGA)-based hardware accelerators. AutoRARE automatically generates all VHDL models needed to build/synthesize a processor specifically tailored for each application. the user needs only provide the VHDL description of a special-purpose floating point Arithmetic logic Unit (ALU) or function core. the tool generates the VHDL description for the memory interface, memory controller, host processor interface, and the application specific processor. We also present details of the FPGA-based multi-memory hardware accelerator for accelerating computationally intensive applications, generated using AutoRARE. the multi-memory hardware accelerator is highly pipelined and able to simultaneously read and write multiple floating point values from multiple memories. the multi-memory architecture is the key to providing hardware accelerators that execute 10X-100X faster than typical multi-core processors. the Taylor Series expansion of the sine/cosine function is used as an application to demonstrate the merits of the multi-memory hardware accelerator. In our experiments, we executed the Taylor Series in software and compared execution times with an FPGA-based hardware implementation. Our experiments show that the FPGA-based multi-memory Taylor Series hardware accelerator is 481X faster than software executing the Taylor Series on a typical server.

关键词： Reconfigurable Computing field-programmable Gate Arrays field-programmable Custom Computing Machines High Performance Computing Multi-Memory Architecture Multiple Memory Banks

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Modular Signal Processing Unit for Motion Control applications Based on System-on-Chip with FPGA

Modular Signal Processing Unit for Motion Control Applicatio...

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international conference on Emerging Technologies and Factory Automation (ETFA)

作者： Vlastimil Šetka Ondřej Ježek Rihards Novickis NTIS – New Technologies for the Information Society Research Center University of West Bohemia Pilsen Czech Republic EDI – Institute of Electronics and Computer Science Riga Latvia

Motion control systems with distributed architecture where multiple input/output devices are connected to the upper layer controller by fast digital communication (fieldbus) became an industrial standard. this paper presents design of a modular input/output device which can process signals from multiple sensors, drive multiple actuators and act as a Slave or Master node in EtherCAT fieldbus network. User-defined algorithms can be easily implemented to preprocess input signals, combine multiple signals or close local control loops with extremely high sampling rates which makes the difference to standard off-the-shelf solutions. To meet these requirements and simplify hardware design, our device is based on System-on-Chip with both programmable logic (FPGA) and classic processor (CPU) ARM cores. Data processing including user algorithms can be done entirely in FPGA which provides very low latency and no jitter, and also on CPU for more complex computations with advantage of tight integration between FPGA and CPU. In this paper we provide description of hardware design, system architecture and typical applications.

关键词： field programmable gate arrays Universal Serial Bus Central Processing Unit Hardware Ethernet Random access memory

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Exploration of Clustering Algorithms effects on Mesh of Clusters based FPGA Architecture Performance

Exploration of Clustering Algorithms effects on Mesh of Clus...

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international conference on High Performance Computing & Simulation (HPCS)

作者： Khouloud Bouaziz Sonda Chtourou Zied Marrakchi Mohamed Abid Abdulfattah Obeid CES Laboratory National School of Engineers of Sfax University of Sfax Sfax Tunisia Mentor Graphics Tunis Tunisia National Center for Electronics and Photonics Technology KACST Riyadh Saudi Arabia

ISBN: (数字)9781728144849

ISBN: (纸本)9781728144856

field programmable Gate Arrays (FPGAs) have become a popular medium for the implementation of many digital circuits. Mapping applications into FPGAs requires a set of efficient Computer-Aided Design (CAD) tools to obtain high-quality Integrated Circuits (ICs). One critical issue of FPGA implementation is the quality and efficiency of associated CAD algorithms. In this paper, we are interested in investigating clustering algorithms aspect to optimize Mesh of Clusters (MoCs) FPGA performance. In fact, the way we distribute logic Blocks (LBs) between FPGA clusters has an important impact on performance. In this paper, we explore the effects of two clustering algorithms (First Choice (FC) and T-VPack) on MoCs FPGA architecture based only on short routing wires. this paper highlights and experimentally demonstrates that FC clustering algorithm ameliorates power consumption, area, critical path delay and energy by an average of 17%, 11%, 13% and 24% respectively compared to T-VPack for MoCs FPGA.

关键词： field programmable gate arrays Clustering algorithms Routing Tools Solid modeling Delays Power demand

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Study Of Fpga-Based Edge Computing In Semiconductor Manufacturing Safety Management Application

Study Of Fpga-Based Edge Computing In Semiconductor Manufact...

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international Microsystems, Packaging, Assembly and Circuits Technology (IMPACT)

作者： Kuo-Chi Chang Kai-Chun Chu Yuh-Chung Lin Hsiao-Chuan Wang Tsui-Lien Hsu Fu-Hsiang Chang Fujian Provincial Key Laboratory of Big Data Mining and Applications Fujian University of Technology Fuzhou China No3 Xueyuan Road University Town Minhou Fuzhou Fujian Province China School of Information Science and Engineering Fujian University of Technology Fuzhou China College of Mechanical & Electrical Engineering National Taipei University of Technology Taipei Taiwan No. 1 Section 3 Zhongxiao East Road Taipei City Taiwan North Borneo University College Sabah Malaysia Lot 47 Block-F Alamesra Permai Plaza 2 Jln Sulaman Kota Kinabalu Sabah Malaysia Fujian University of Technology Fuzhou China Institute of Environmental Engineering National Taiwan University Taipei Taiwan No.1 Section 4 Roosevelt Road Taipei City Taiwan Institute of Construction Engineering and Management National Central University Taoyuan Taiwan No. 300 Zhongda Rd. Zhongli District Taoyuan City Taiwan Shih-Hsin University Taipei Taiwan No. 1 Ln. 17 Sec. 1 Muzha Rd. Wenshan Dist. Taipei City Taiwan

ISBN: (数字)9781728198514

ISBN: (纸本)9781728198521

this study is based on the LOPA and ISD strategies as the basis for safety management, and explores the edge computing solutions that are extended in response to the vigorous development of 5G and IoT in the future, resulting in excessive cloud computing load. this study mainly uses FPGA to combine AES algorithm to achieve the edge computing function based on the aforementioned LOPA and ISD strategies for safety management under big data. However, the results of this study found that the system established in this study can effectively reduce the personnel management error rate by more than 50% and reduce the cloud computing load by 30%. High-tech factory operation safety management has significant benefits and contributions.

关键词： Ions Urban areas Tin Safety management Manufacturing Legged locomotion field programmable gate arrays

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An Embeddings Based Fuzzy Linguistics Supported Model to Measure the Contextual Bias in Sentiment Polarity 17

An Embeddings Based Fuzzy Linguistics Supported Model to Mea...

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17th international conference on New Trends in Intelligent Software Methodology Tools, and Techniques (SoMeT)

作者： Bernabe-Moreno, Juan Tejeda-Lorente, Alvaro Herce-Zelaya, Julio Porcel, Carlos Herrera-Viedma, Enrique Univ Granada Dept Comp Sci & Artificial Intelligence Granada Spain Univ Jaen Dept Comp Sci Jaen Spain

ISBN: (纸本)9781614999003;9781614998990

Polarity detection plays a pivotal role in the modern cognitive research field. Common approaches to compute the polarity of a given word rely on experimental dictionaries providing always the same value, no matter where the word is used and lacking therefore adaptivity to particular contexts. In a previous article, we proposed a method supported by fuzzy linguistic modelling to quantify this contextual bias and to enable the bias -aware sentiment analysis. In this work, we implement the bias contextualization based on a word embeddings technique to capture a larger portion of the contextual bias. To show how our approach works, we measure the bias of common concepts in two different domains and discuss the results compared with our previous attempt based on document contextualization.

关键词： sentiment analysis polarity linguistic modelling fuzzy logic contextual bias word embeddings deep learning

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Implementation of high-performance floating point divider using pipeline architecture on FPGA 1

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6th international conference on Frontiers of Intelligent Computing: theory and applications, FICTA-2017

作者： Hanuman, C.R.S. Kamala, J. Department of Electronics and Communication Engineering College of Engineering Guindy Anna University Chennai India

ISBN: (数字)9789811075667

ISBN: (纸本)9789811075650

Data intensive DSP algorithms mostly depend on double precision (DP) floating point arithmetic operations. With advanced FPGA devices, applications need more floating point arithmetic operations to accelerate reconfigurable logic. Important and complex applications heavily depend on the floating point divider (FPD) blocks. this paper illustrates implementation of low-latency dividers based on pipelining, which is operated at 30% faster than existing divider. DPFPD implemented using field programmable gate array (FPGA) outperforms other ULP dividers. Pipelining architecture of FPD increases the throughput and reduces the power considerably. the architecture is validated for standalone as well as integrated application levels. © Springer Nature Singapore Pte Ltd. 2018.

关键词： field programmable gate arrays (FPGA)

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