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检索条件"任意字段=17th International Conference on Field Programmable Logic and Applications"

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A Security Library for FPGA Interlays 27

A Security Library for FPGA Interlays

引用

27th international conference on field programmable logic and applications (FPL)

作者： Vaishnav, Anuj Ordaz, Jose Raul Garcia Koch, Dirk Univ Manchester Sch Comp Sci Manchester Lancs England

ISBN: (纸本)9789090304281

Many CPU design houses have added dedicated support for cryptography in recent processor generations, including Intel, IBM, and ARM. While adding accelerators and/or dedicated instructions boosts performance on cryptography, we are investigating a different approach that is not adding extra silicon area: We study to replace the hardened NEON SIMD unit of an ARM Cortex-A9 with an identical sized FPGA fabric, called an interlay. this will be used for implementing cryptographic instructions in soft-logic. We show that this approach can outperform the hardened NEON by up to 7.7 x on AES and provide functionality that is not available in the hardened ARM.

关键词： Neon field programmable gate arrays Cryptography Pipeline processing Fabrics Table lookup throughput

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Optimizing Streaming Stencil Time-step Designs via FPGA Floorplanning 27

Optimizing Streaming Stencil Time-step Designs via FPGA Floo...

引用

27th international conference on field programmable logic and applications (FPL)

作者： Rabozzi, Marco Natale, Giuseppe Festa, Biagio Miele, Antonio Santambrogio, Marco D. Politecn Milan Milan Italy

ISBN: (纸本)9789090304281

Stencil computations represent a highly recurrent class of algorithms in various high performance computing scenarios. the Streaming Stencil Time-step (SST) architecture is a recent implementation of stencil computations on field programmable Gate Array (FPGA). In this paper, we propose an automated framework for SST-based architectures capable of achieving the maximum performance level for a given FPGA device through 1) the maximization of basic modules instantiated in the design and 2) optimization of the design floorplanning. Experimental results show that the proposed approach reduces the design time up to 15x w.r.t. naive design space exploration approaches, and improves the performance of the 13%.

关键词： field programmable Gate Arrays Floorplanning Stencil Computations

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FISH: Linux System Calls for FPGA Accelerators 27

FISH: Linux System Calls for FPGA Accelerators

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27th international conference on field programmable logic and applications (FPL)

作者： Nam, Kevin Fort, Blair Brown, Stephen Univ Toronto ECE Dept Toronto ON Canada

ISBN: (纸本)9789090304281

this paper presents the FISH (FPGA-Initiated Software-Handled) framework which allows FPGA accelerators to make system calls to the Linux operating system in CPU-FPGA systems. A special FISH Linux kernel module running on the CPU provides a system call interface for FPGA accelerators, much like the ABI which exists for software programs. We provide a proofof-concept implementation of this framework running on the Intel Cyclone V SoC device, and show that an FPGA accelerator can seamlessly make system calls as if it were the host program. We see the FISH framework being especially useful for high-level synthesis (HLS) by making it possible to synthesize software code that contains system calls.

关键词： Fish Kernel Linux field programmable gate arrays Registers Acceleration

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FPGA Implementation of Edge-Guided Pattern Generation for Motion-Vector Estimation of Textureless Objects 27

FPGA Implementation of Edge-Guided Pattern Generation for Mo...

引用

27th international conference on field programmable logic and applications (FPL)

作者： Tanibata, Aoi Schmid, Alexandre Takamaeda-Yamazaki, Shinya Ikebe, Masayuki Motomura, Masato Asai, Tetsuya Hokkaido Univ Grad Sch Informat Sci & Technol Kita Ku Kita 19Nishi 9 Sapporo Hokkaido 0600814 Japan Ecole Polytech Fed Lausanne Microelect Syst Lab CH-1015 Lausanne Switzerland

ISBN: (纸本)9789090304281

the widely accepted block-matching technique, which is required to identify motion vectors, fails in cases in which texture is not existent. In [1], we proposed a hardware-oriented cellular-automaton algorithm that generates spatial patterns on textureless objects and backgrounds, aiming at motion-vector estimation of textureless moving objects. this demonstration presents a field-programmable gate array (FPGA) system that supports real-time processing. this system provides motion-vectors in moving textureless objects and enables enhanced processing of motion vector classification.

关键词： Estimation Computer architecture Prototypes field programmable gate arrays Real-time systems Cameras Information science

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Tectogrammatical Trees and Fuzzy Natural logic in Linguistic Characterization of Dynamic Processes 17

Tectogrammatical Trees and Fuzzy Natural Logic in Linguistic...

引用

Joint 17th World Congress of international-Fuzzy-Systems-Association / 9th international conference on Soft Computing and Intelligent Systems (IFSA-SCIS)

作者： Novak, Vilem Univ Ostrava Inst Res & Applicat Fuzzy Modeling NSC IT4Innovat 30Dubna 22 Ostrava 70103 1 Czech Republic

ISBN: (纸本)9781509049172

this paper is a contribution to the applications of fuzzy logic in modeling of linguistic semantics. the topic of interest is description of the past course of a dynamical process that is given by data in the form of time series. We suggest to use the well developed technique of linguistic theory, the so called tectogrammatical trees using which linguists represent semantics of sentences. the core of the suggested procedure is construction of the tectogrammatical tree that is then assigned a formula of fuzzy natural logic. As the latter construes semantics of the given sentence, we can construct a model on the basis of the given data. If successful, the initial sentence can be taken as a linguistic characterization of them. In this paper we demonstrate how sentences characterizing the course of the trend of time series can be assigned the formulas of fuzzy natural logic expressing their semantics via tectogrammatical trees.

关键词： Estimation field programmable gate arrays OFDM Modulation Filtration Clocks Signal processing algorithms

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Accelerated analysis of Boolean gene regulatory networks 27

Accelerated analysis of Boolean gene regulatory networks

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27th international conference on field programmable logic and applications (FPL)

作者： Purandare, Mitra Polig, Raphael Hagleitner, Christoph IBM Res Zurich Zurich Switzerland

ISBN: (纸本)9789090304281

In Systems Biology, Boolean models are gaining popularity in modeling and analysis of qualitative dynamics of gene regulatory mechanisms. With the development of advanced high-throughput technologies, the availability of experimental data on gene-gene, gene-protein interactions is ever increasing. Consequently, modern Boolean models are increasing in size and complexity. Software simulation of Boolean models does not scale for such state-of-the-art complex Boolean models. We propose field programmable Gate Arrays (FPGAs) for emulation of Boolean models, exploiting the highly parallel nature of FPGAs. Our emulation framework consists of converting a Boolean model to Verilog, connecting it to an execution core, which runs on an FPGA coherently attached to a POWER8 processor. We report an order of magnitude speed up over a multi-threaded software simulation tool running on the same processor.

关键词： Biological system modeling Registers field programmable gate arrays Software Mathematical model Computational modeling Clocks

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Application-Specific Soft-Core Vector Processor for Advanced Driver Assistance Systems 27

Application-Specific Soft-Core Vector Processor for Advanced...

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27th international conference on field programmable logic and applications (FPL)

作者： Nolting, Stephan Giesemann, Florian Hartig, Julian Schmider, Achim Paya-Vaya, Guillermo Leibniz Univ Hannover Inst Microelect Syst Appelstr 4 D-30167 Hannover Germany

ISBN: (纸本)9789090304281

Implementing convolutional neural networks for scene labelling is a current hot topic in the field of advanced driver assistance systems. the massive computational demands under hard real-time and energy constraints can only be tackled using specialized architectures. Also, cost-effectiveness is an important factor when targeting lower quantities. In this PhD thesis, a vector processor architecture optimized for FPGA devices is proposed. Amongst other hardware mechanisms, a novel complex operand addressing mode and an intelligent DMA are used to increase perfromance. Also, a C-compiler support for creating applications is introduced.

关键词： field programmable gate arrays Random access memory Computer architecture Vector processors Advanced driver assistance systems Biological neural networks Parallel processing

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In-Network Online Data Analytics with FPGAs 27

In-Network Online Data Analytics with FPGAs

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27th international conference on field programmable logic and applications (FPL)

作者： Cooke, Ryan Fahmy, Suhaib A. Univ Warwick Sch Engn Coventry W Midlands England

ISBN: (纸本)9789090304281

the growth of sensor technology, communication systems and computation have led to vast quantities of data being available for relevant parties to utilise. applications such as the monitoring and analysis of industrial equipment, smart surveillance, and fraud detection rely on the ‘real-time’ analysis of time sensitive data gathered from distributed sources. A variety of processing tasks, such as filtering, aggregation, machine learning algorithms, or other transformations to be carried out on this data in order to extract value from it. Centralised computation strategies are often deployed in these scenarios, with the majority of the data being forwarded though the network to a datacenter environment, typically due to the lack of required computational or storage resources at the leaves of the network, and data from other sources or historical data being required. this approach has also traditionally been viewed as more scalable, as resources can be augmented through the addition of extra compute hardware and cloud services.

关键词： field programmable gate arrays Hardware Computational modeling Drones Bandwidth Real-time systems

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Evaluating FPGA Clusters under Wide Ranges of Design Parameters 27

Evaluating FPGA Clusters under Wide Ranges of Design Paramet...

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27th international conference on field programmable logic and applications (FPL)

作者： Zgheib, Grace Ienne, Paolo Ecole Polytech Fed Lausanne Sch Comp & Commun Sci CH-1015 Lausanne Switzerland

ISBN: (纸本)9789090304281

the latest published studies with extensive explorations of look-up table and cluster sizes are now more than a decade old. However, CMOS technology as well as CAD and transistor modeling tools have improved so much since that it is reasonable to wonder whether the conclusions of such studies still hold. One of the major difficulties of conducting these studies, especially in academia, is producing credible delay and area models. In this paper, we take advantage of a recently developed architecture modeling tool to re-evaluate the effect of the various cluster parameters on the FPGA. We considerably extend the exploration space beyond that of the classic studies to include sparse crossbars and fracturable LUTs, and show some results that go against the current tenets of FPGA architecture.

关键词： Solid modeling Table lookup field programmable gate arrays Tools Routing Delays

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Dynamic Bitwidth Assignment for Efficient Dot Products 27

Dynamic Bitwidth Assignment for Efficient Dot Products

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27th international conference on field programmable logic and applications (FPL)

作者： Schmidt, Simon Joel Boland, David Monash Univ Dept Elect & Comp Syst Engn Clayton Vic Australia Univ Sydney Sch Elect & Informat Engn Sydney NSW Australia

ISBN: (纸本)9789090304281

the benefits of customising the precision throughout an FPGA design according to a design tolerance are well known. However, customising the precision of a design at run-time has the potential for an even greater performance impact. In this paper, we add the ability to dynamically choose the internal precision of a datapath. this enables a result that is at least as accurate as the worst-case under standard precisions, whilst internally operating at a lower precision. We demonstrate this technique on fused floating-point dot-product circuits. We show that for circuits with inputs that have a wide dynamic range, we can see substantial resource savings. We provide examples with savings of up to 75% of the DSPs and 16% of the ALMs over an optimised fused dot-product design.

关键词： Multiplexing Random access memory Algorithm design and analysis Adders Clocks field programmable gate arrays Hardware

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