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A Partial Reconfiguration based Microphone Array Network Emulator 27

A Partial Reconfiguration based Microphone Array Network Emu...

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27th international conference on field programmable logic and applications (FPL)

作者： da Silva, Bruno Dominguez, Federico Braeken, An Touhafi, Abdellah Vrije Univ Brussel Dept Ind Sci INDI Brussels Belgium Escuela Super Politecn Litoral ESPOL Guayaquil Ecuador

ISBN: (纸本)9789090304281

Nowadays, microphone arrays are used in many applications for sound-source localization or acoustic enhancement. the current Micro-Electro-Mechanical Systems (MEMS) technology allows the development of networks of microphone arrays at a relatively low cost. Unfortunately, the evaluation of these networks requires controlled acoustic environments, such as anechoic chambers, to avoid possible distortions and acoustic artifacts. In this paper, we present a partial reconfigurable FPGA platform to emulate a network of microphone arrays. Our platform provides a controlled simulated acoustic environment, able to evaluate the impact of different network configurations such as the number of microphones per array, the network's topology or the used detection method. Data fusion techniques, combining the data collected by each node, are used in this platform. In addition, our platform is also capable to converge to the ideal network with regards to power consumption, while still maintaining the desired level of sound-source localization accuracy. A graphical user interface provides a friendly control of the network and the parameters under test during the execution of the partial reconfiguration operations. Several experiments are presented to demonstrate some of the capabilities of our platform.

关键词： field programmable gate arrays Microphone arrays Acoustics Data integration Computer architecture Acoustic arrays

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Latency-Driven Design for FPGA-based Convolutional Neural Networks 27

Latency-Driven Design for FPGA-based Convolutional Neural Ne...

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27th international conference on field programmable logic and applications (FPL)

作者： Venieris, Stylianos I. Bouganis, Christos-Savvas Imperial Coll London Dept Elect & Elect Engn London England

ISBN: (纸本)9789090304281

In recent years, Convolutional Neural Networks (ConvNets) have become the quintessential component of several state-of-the-art Artificial Intelligence tasks. Across the spectrum of applications, the performance needs vary significantly, from high-throughput image recognition to the very low-latency requirements of autonomous cars. In this context, FPGAs can provide a potential platform that can be optimally configured based on different performance requirements. However, with the increasing complexity of ConvNet models, the architectural design space becomes overwhelmingly large, asking for principled design flows that address the application-level needs. this paper presents a latency-driven design methodology for mapping ConvNets on FPGAs. the proposed design flow employs novel transformations over a Synchronous Dataflow-based modelling framework together with a latency-centric optimisation procedure in order to efficiently explore the design space targeting low-latency designs. Quantitative evaluation shows large improvements in latency when latency-driven optimisation is in place yielding designs that improve the latency of AlexNet by 73.54x and VGG16 by 5.61x over throughput-optimised designs.

关键词： field programmable gate arrays Feature extraction Space exploration Computational modeling Machine learning Convolution Biological system modeling

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REAPR: Reconfigurable Engine for Automata Processing 27

REAPR: Reconfigurable Engine for Automata Processing

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27th international conference on field programmable logic and applications (FPL)

作者： Xie, Ted Dang, Vinh Wadden, Jack Skadron, Kevin Stan, Mircea Univ Virginia Dept Elect & Comp Engn Charlottesville VA 22903 USA Univ Virginia Dept Comp Sci Charlottesville VA 22903 USA

ISBN: (纸本)9789090304281

Finite automata have proven their usefulness in high-profile domains ranging from network security to machine learning. While prior work focused on their applicability for purely regular expression workloads such as antivirus and network security rulesets, recent research has shown that automata can optimize the performance for algorithms in other areas such as machine learning and even particle physics. Unfortunately, their emulation on traditional CPU architectures is fundamentally slow and further bottlenecked by memory. In this paper, we present REAPR: Reconfigurable Engine for Automata PRocessing, a flexible framework that synthesizes RTL for automata processing applications as well as I/O to handle data transfer to and from the kernel. We show that even with memory and control flow overheads, FPGAs still enable extremely high-throughput computation of automata workloads compared to other architectures.

关键词： Automata field programmable gate arrays Engines Learning automata Benchmark testing Computer architecture

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Versatile Deployment of FPGA Accelerators in Disaggregated Data Centers: a Bioinformatics Case Study 27

Versatile Deployment of FPGA Accelerators in Disaggregated D...

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27th international conference on field programmable logic and applications (FPL)

作者： Alachiotis, Nikolaos theodoropoulos, Dimitris Pnevmatikatos, Dionisios Fdn Res & Technol Hellas Inst Comp Sci Iraklion 70013 Greece Tech Univ Crete Sch Elect & Comp Engn Khania 73100 Greece

ISBN: (纸本)9789090304281

Important design considerations for the cost-effective employment of hardware accelerators in next-generation data centers involve a) the type of candidate applications that a proposed solution can accelerate (generality), and b) the required development effort to successfully deploy the available accelerators for a given application (adoption overhead). To address the problem of generality, we present a versatile and dynamically reconfigurable hardware architecture that exhibits several accelerator slots and programmable interconnect to create application-specific accelerator datapaths. the proposed architecture fits in the model of disaggregated data centers, where compute, memory, and accelerators are broadly regarded as large pools of resources, and subsets of these resource pools are dynamically allocated on an as-needed basis to cooperatively boost performance of a broad range of applications. Initial results for a bioinformatics application that we employ as a case study and deals with the detection of positive selection in large-scale genomic datasets reveal a speedup of up to 6.4X when custom hardware accelerators are mapped to the proposed versatile accelerator architecture and compared with a parallel and highly optimized software implementation executed on a multi-core processor.

关键词： Hardware Acceleration Computer architecture field programmable gate arrays Genomics Bioinformatics

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Vivado Design Interface: An Export/Import Capability for Vivado FPGA Designs 27

Vivado Design Interface: An Export/Import Capability for Viv...

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27th international conference on field programmable logic and applications (FPL)

作者： Townsend, thomas Nelson, Brent Brigham Young Univ Dept Elect & Comp Engn NSF Ctr High Performance Reconfigurable Comp CHRE Provo UT 84602 USA

ISBN: (纸本)9789090304281

Research tools targeting commercial FPGAs have most commonly been based on the Xilinx Design Language (XDL). Vivado, however, does not support XDL, preventing similar tools from being created for next-generation devices. Instead, Vivado includes a Tcl interface that exposes Xilinx's internal design and device data structures. Considerable challenges still remain to users attempting to leverage this Tcl interface to develop external CAD tools. this paper presents the Vivado Design Interface (VDI), a set of file formats and Tcl functions that address the challenges of exporting and importing designs to and from Vivado. To demonstrate its use, VDI has been integrated with RapidSmith2, an external FPGA CAD framework. To our knowledge this work is the first successful attempt to provide an open-source tool-flow that can export designs from Vivado, manipulate them with external CAD tools, and re-import an equivalent representation back into Vivado.

关键词： Tools Computer architecture Routing Microprocessors field programmable gate arrays Pins Wires

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High throughput AES Encryption/Decryption with Efficient Reordering and Merging Techniques 27

High Throughput AES Encryption/Decryption with Efficient Reo...

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27th international conference on field programmable logic and applications (FPL)

作者： Li, Lijuan Li, Shuguo Tsinghua Univ Inst Microelect Beijing Peoples R China

ISBN: (纸本)9789090304281

this paper proposes a high throughput architecture for AES encryption/decryption targeting on the recent FPGAs with 6-input LUTs. Unlike previous works which share multiplicative inverse logics to realize SubBytes and InvSubBytes, the proposed architecture directly employs the look-up-table based Sbox for both SubBytes and InvSubBytes. Efficient reordering and merging techniques are applied to achieve a highly integrated encryption/decryption datapath with reduced area and delay. By sharing Sbox instead of inversion, the encryption datapath remains simple with unchanged MixColumns. For decryption, the linear operations including two inverse Affine functions and InvMixColumns between SubBytes are merged into a new InvMixColumns (NIMC-I) transformation. the NIMC-I is further optimized to reduce resources and share logics with MixColumns. through loop-unrolling and fair pipelining, the proposed 3-stage subpipelined design achieves 68.82 Gbps on XC7VX330T using 3930 slices and the 5-stage deep-pipelined one achieves 76.19 Gbps on XC6VLX240T using 4426 slices, which outperform previous equivalent designs in terms of throughput per area.

关键词： Encryption field programmable gate arrays throughput Merging Table lookup Pipeline processing

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Quantifying and Mitigating the Costs of FPGA Virtualization 27

Quantifying and Mitigating the Costs of FPGA Virtualization

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27th international conference on field programmable logic and applications (FPL)

作者： Yazdanshenas, Sadegh Betz, Vaughn Univ Toronto Dept Elect & Comp Engn Toronto ON Canada

ISBN: (纸本)9789090304281

FPGAs are being incorporated into contemporary datacenters in order to improve computational capacity, power consumption, and processing latency. Efficiently integrating FPGAs in datacenters is, however, quite challenging. Ideally, smaller tasks could share a device and the cloud management layer would be able to partially reconfigure the device to allocate its free resources to incoming tasks. Moreover, to facilitate FPGA hardware upgrades without undue porting effort for previously developed accelerator tasks, the complexities associated with board-specific system-level integration should be abstracted away from designers. By meeting these requirements, FPGAs in the cloud would become multi-user virtualized resources with increased availability and elasticity. the virtualization of FPGAs, however, comes with two major costs in current FPGAs: lower application operating frequency, and extravagant use of routing resources. In this paper, we quantify the costs of FPGA virtualization and demonstrate that for an FPGA that supports four independent tasks, virtualization reduces the task average frequency by 18% to 46% and increases wire usage to 2.6x. We also investigate the cause of these costs and show that the use of hard NoCs in future datacenter-optimized FPGAs would facilitate FPGA virtualization without sacrificing operating frequency or routing resources.

关键词： field programmable gate arrays Virtualization Routing Bandwidth Cloud computing Random access memory

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Customised Pearlmutter Propagation: A Hardware Architecture for Trust Region Policy Optimisation 27

Customised Pearlmutter Propagation: A Hardware Architecture ...

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27th international conference on field programmable logic and applications (FPL)

作者： Shao, Shengjia Luk, Wayne Imperial Coll London Dept Comp London England

ISBN: (纸本)9789090304281

Reinforcement Learning (RL) is an area of machine learning in which an agent interacts with the environment by making sequential decisions. the agent receives reward from the environment to find an optimal policy that maximises the reward. Trust Region Policy Optimisation (TRPO) is a recent policy optimisation algorithm that achieves superior results in various RL benchmarks, but is computationally expensive. this paper proposes Customised Pearlmutter Propagation (CPP), a novel hardware architecture that accelerates TRPO on FPGA. We use the Pearlmutter Algorithm to address the key computational bottleneck of TRPO in a hardware efficient manner, avoiding symbolic differentiation with change of variables. Experimental evaluation using robotic locomotion benchmarks demonstrates that the proposed CPP architecture implemented on Stratix-V FPGA can achieve up to 20 times speed-up against 6-threaded Keras deep learning library with theano backend running on a Core i7-5930K CPU.

关键词： Hardware field programmable gate arrays Optimization Machine learning Computer architecture Benchmark testing Acceleration

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PAAS: A System Level Simulator for Heterogeneous Computing Architectures 27

PAAS: A System Level Simulator for Heterogeneous Computing A...

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27th international conference on field programmable logic and applications (FPL)

作者： Liang, Tingyuan Feng, Liang Sinha, Sharad Zhang, Wei Hong Kong Univ Sci & Technol Dept Elect & Comp Engn Hong Kong Hong Kong Peoples R China Nanyang Technol Univ Sch Comp Sci & Engn Singapore Singapore

ISBN: (纸本)9789090304281

Heterogeneous computing with hardware accelerators is a promising direction to overcome the power and performance walls in traditional computing systems. CPU-accelerator integrated architectures, such as CPU with ASIC or FPGA based accelerators, are able to provide customized processing according to application requirements and are thus particularly attractive to speed up computation-intensive applications. therefore, system level simulation showing the interaction among CPUs, hardware accelerators and memory system precisely is important for performing design space exploration leading to architecture and design optimization. In this work, we present PAAS (Processor Accelerator Architecture Simulator), a system level simulator to enable cycle-accurate full system simulation of CPU-accelerator heterogeneous systems. PAAS can easily support flexible architectural configurations, such as different on-chip interconnection topologies, memory hierarchy, etc. Using PAAS, this paper also presents the analysis of the impact of different architectural configurations on the performance of benchmark applications with different execution characteristics using FPGA based accelerators. Furthermore, as an example showing the research capability of PAAS, this paper proposes and investigates a cache-partitioning scheme for improving the performance of shared-cache based CPU-FPGA systems.

关键词： field programmable gate arrays Registers Hardware Hardware design languages Ports (Computers) Monitoring

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Accelerator-in-Switch: a framework for tightly coupled switching hub and an accelerator with FPGA 27

Accelerator-in-Switch: a framework for tightly coupled switc...

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27th international conference on field programmable logic and applications (FPL)

作者： Tsuruta, Chiharu Kaneda, Takahiro Nishikawa, Naoki Amano, Hideharu Keio Univ Dept Informat & Comp Sci Yokohama Kanagawa Japan

ISBN: (纸本)9789090304281

Accelerator-in-Switch (AiS) is a framework for building an accelerator logic tightly coupled with a switching hub in a single FPGA for high performance computation with heterogeneous environment with CPUs and GPUs. AiS is implemented on a partial reconfigurable region of an FPGA whose permanent region is used for a switching hub. A port of the switching hub is connected to the registers and local memory of AiS directly. AiS has a standard interface for a standard bus (Avalon MM bus, here) to exchange data between on-board DDR SDRAM and the local memory, and various types of accelerators can be implemented just by providing such an interface. the data input and output are performed with the DMA controller inside the switching hub with the shared memory model between host CPUs and GPUs. We implemented two example accelerators: a reduction calculator for a radiation transfer equations solver (RED) and LET generator for N-body simulation (LET) were implemented as the AiS on PEACH3, a switching hub for a PCIe direct interconnection network with Altera's Stratix V. the use of partial reconfiguration makes it possible to switch multiple accelerators without stopping the switching hub. As a result, we reduced the time for place&route of an accelerator by 47% compared to the case of the design combining the accelerator into the switching hub.

关键词： Switches field programmable gate arrays Ports (Computers) SDRAM Calculators IP networks Hardware

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