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检索条件"任意字段=17th International Conference on Field Programmable Logic and Applications"

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Learning-based Interconnect-aware Dataflow Accelerator Optimization 27

Learning-based Interconnect-aware Dataflow Accelerator Optim...

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27th international conference on field programmable logic and applications (FPL)

作者： Liu, Shuangnan Schafer, Benjamin Carrion Hong Kong Polytech Univ Dept Elect & Informat Engn Kowloon Hong Kong Peoples R China Univ Texas Dallas Dept Elect & Comp Engn 800 W Campbell Rd Richardson TX 78050 USA

ISBN: (纸本)9789090304281

the interconnect is the Achilles heel of FPGAs. It currently dominates the delay and leads to high power consumption. It is thus, imperative to take it into account when designing complex FPGA systems. In this work, we propose a learning-based method for data-flow systems build out of multiple individual components directly connected and find a set of optimal configurations with unique area vs. throughput trade-offs by time-multiplexing their interconnects. these type of configurations are prevalent in FPGA designs where one block streams data to the next one, i.e., jpeg encoders. One uniqueness of this work is that it uses advanced features of state-of-the-art HLS tools that enable automatic pin multiplexing. this feature implies that logic IO ports are time multiplexed automatically, which affects not only the performance of the design, but also the area, and the interconnect complexity, leading to system configurations with unique area vs. performance trade-offs. Pin multiplexing is not feasible at the RT-level where each design has to be manually optimized. Experimental results show that the method is accurate and fast when compared to an exhaustive search as well as other state-of-the-art methods.

关键词： Pins throughput Delays Multiplexing field programmable gate arrays Ports (Computers) Integrated circuit interconnections

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Fast RNS Implementation of Elliptic Curve Point Multiplication in GF(p) with Selected Base Pairs 27

Fast RNS Implementation of Elliptic Curve Point Multiplicati...

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27th international conference on field programmable logic and applications (FPL)

作者： Mo, Yifeng Li, Shuguo Tsinghua Univ Inst Microelect Tsinghua Natl Lab Informat Sci & Technol Beijing Peoples R China

ISBN: (纸本)9789090304281

Implementing elliptic curve point multiplication (ECPM) based on residue number system (RNS) can efficiently use FPGA resources. In this paper, we propose a modular reduction method, where a kind of RNS pair is selected to achieve fast reduction. Our reduction method mainly needs several parallel additions while the reduction unit of previous designs require two multiplications which are computed serially. We also present a novel multiplier-and-accumulator (MAC) with modular reduction unit (MAAU), whose reduction unit employs our fast reduction method, and MAC is based on Karatsuba-Ofman method. Compared with the previous classic designs based on Cox-Rower architecture, our reduction method allows our MAAU to take much larger radix r = 6 6 without increasing the number of the pipeline stages of MAAU while clock frequency keeps relatively high and no more resources are consumed. Taking larger radix leads to reducing the number of modulo, thus reducing the number of the required cycles and accelerating ECPM. Experimental results obtained on FPGA Stratix II show that the point multiplication for any curves of the size 256, 384 and 521 can be accomplished in 0.42, 0.87 and 1.53 ms respectively, which outperform the previous designs.

关键词： Pipelines Computer architecture Clocks Delays Elliptic curves Adders field programmable gate arrays

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Comparison of Hardware and Software Implementations of Selected Lightweight Block Ciphers 27

Comparison of Hardware and Software Implementations of Selec...

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27th international conference on field programmable logic and applications (FPL)

作者： Diehl, William Farahmand, Farnoud Yalla, Panasayya Kaps, Jens-Peter Gaj, Kris George Mason Univ Dept Elect & Comp Engn Fairfax VA 22030 USA

ISBN: (纸本)9789090304281

Lightweight block ciphers are an important topic of research in the context of the Internet of things (IoT). Current cryptographic contests and standardization efforts seek to benchmark lightweight ciphers in both hardware and software. Although there have been several benchmarking studies of both hardware and software implementations of lightweight ciphers, direct comparison of hardware and software implementations is difficult due to differences in metrics, measures of effectiveness, and implementation platforms. In this research, we facilitate this comparison by use of a custom lightweight reconfigurable processor. We implement six ciphers, AES, SIMON, SPECK, PRESENT, LED and TWINE, in hardware using register transfer level (RTL) design, and in software using the custom reconfigurable processor. Both hardware and software implementations are instantiated in identical Xilinx Kintex-7 FPGAs, which enables direct comparison of throughput, area, throughput-to-area (TP/A) ratio, power, and energy. Results show that TWINE and AES have the highest TP/A ratios for hardware and software implementations, respectively, assuming an area target of 300 - 450 LUTs. In terms of direct comparison, software implementations on tailored reconfigurable processers generally use less power - especially where reconfigurable instruction set extensions are permitted. However, custom hardware implementations have higher throughput and energy-efficiency than software implementations on the same platform.

关键词： Cipher cryptography encryption field programmable gate array reconfigurable microcontroller

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OpenSoC System Architect: An Open Toolkit for Building Soft-Cores on FPGAs 27

OpenSoC System Architect: An Open Toolkit for Building Soft-...

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27th international conference on field programmable logic and applications (FPL)

作者： Fatollahi-Fard, Farzad Donofrio, David Shalf, John Leidel, John Wang, Xi Chen, Yong Lawrence Berkeley Natl Lab Berkeley CA 94720 USA Tact Comp Labs Dallas TX USA Texas Tech Univ Lubbock TX 79409 USA

ISBN: (纸本)9789090304281

Given the recent difficulty in continuing the classic CMOS manufacturing density and power scaling curves, also known as Moore's Law and Dennard Scaling, respectively, we find that modern complex system architectures are increasingly relying upon accelerators in order to optimize the placement of specific computational workloads. In addition, large-scale computing infrastructures utilized in HPC, data intensive computing, and cloud computing must rely almost exclusively upon commodity device architectures provided by third-party manufacturers. the end result being a final system architecture that lacks specificity for the target software workload. At the same time, there is a trend in the FPGA space of much larger FPGAs with a lot more resources and hardened IP blocks, making this type of architecture design space exploration much easier. the OpenSoC System Architect infrastructure combines several open source design tools and methodologies into a central infrastructure for designing, developing, and verifying the necessary hardware and software modules required to implement application-specific processors for use in FPGAs. the end result is an infrastructure that permits rapid development and deployment of application-specific accelerators and softcores, including a fully functional software development tool chain.

关键词： field programmable gate arrays Hardware Software Tools Computer architecture Standards Market research

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Area-optimized Montgomery multiplication on IGLOO 2 FPGAs 27

Area-optimized Montgomery multiplication on IGLOO 2 FPGAs

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27th international conference on field programmable logic and applications (FPL)

作者： Massolino, Pedro Maat C. Batina, Lejla Chaves, Ricardo Mentens, Nele Radboud Univ Nijmegen iCIS Digital Secur Grp Nijmegen Netherlands Univ Lisbon INESC ID IST Lisbon Portugal Katholieke Univ Leuven Imec COSIC Leuven Belgium

ISBN: (纸本)9789090304281

this paper presents the first area-optimized Montgomery modular multiplication module on low-power reconfigurable IGLOO((R)) 2 FPGAs, from Microsemi. In order to obtain a good response time with few resources, the FPGA pipelined Math blocks and the embedded memory blocks are fully leveraged. As a result, 256-bit modular multiplications can be done in 2.33 mu s, at a cost of 505 LUT4 cells, 257 Flip Flops, 1 Math block and 1 64x18 RAM block. If more area resources are considered, a modular multiplication can be performed in 1.25 mu s at a cost of 680 LUT4s, 341 Flip Flops, 2 Math blocks and 2 64x18 RAM blocks. this work is the first fundamental step towards area-efficient public-key cryptography on the Microsemi IGLOO((R)) 2 FPGAs.

关键词： field programmable gate arrays Random access memory Algorithm design and analysis Pipelines Table lookup Galois fields Digital signal processing

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Deflection-Routed Butterfly Fat Trees on FPGAs 27

Deflection-Routed Butterfly Fat Trees on FPGAs

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27th international conference on field programmable logic and applications (FPL)

作者： Kapre, Nachiket Univ Waterloo Waterloo ON Canada

ISBN: (纸本)9789090304281

Bufferless, deflection-routed, Butterfly Fat Trees (BFTs) can outperform state-of-the-art FPGAs overlay NoCs such as Hoplite by as much as 2-5 x on throughput and approximate to 5 x on worst-case latency at identical PE counts, and by approximate to 1.5 x on throughput at identical resource costs > 16K LUTs for statistical traffic patterns. In this paper, we show how to modify the tree connectivity and routing function to support deflection routing on the BFT topology. We introduce the idea of localized deflections that trap deflected packets within a single level of a multi-level BFT to avoid the long round-trip penalty traditionally associated with deflection routing. Across a range of statistical traffic patterns, we show a sustained throughput improvement of 2-5 x over for Hoplite for system sizes as large at 512 PEs at above 20% injection rates when using localized deflections. We also show how the configurable bisection bandwidth of the BFT, modeled with the Rent parameter 0the best performing NoC at a desired cost. For instance, our NoC generator can produce simple trees (P=0) for low-cost applications <2K LUTs, mesh-equivalent BFTs (P=0.5) for real-world applications with locality at <10K LUTs, and crossbars (P=1) when cost is not a constraint >64K LUTs. For workloads with locality, we recommend the BFT topology with p = 0.67.

关键词： Switches Routing Topology field programmable gate arrays Bandwidth Table lookup Fats

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Decision Tree Based Hardware Power Monitoring for Run Time Dynamic Power Management in FPGA 27

Decision Tree Based Hardware Power Monitoring for Run Time D...

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27th international conference on field programmable logic and applications (FPL)

作者： Lin, Zhe Zhang, Wei Sharad, Sinha Hong Kong Univ Sci & Technol Dept Elect & Comp Engn Hong Kong Hong Kong Peoples R China Nanyang Technol Univ Sch Comp Engn Singapore Singapore

ISBN: (纸本)9789090304281

Fine-grained runtime power management techniques could be promising solutions for power reduction. therefore, it is essential to establish accurate power monitoring schemes to obtain dynamic power variation in a short period (i.e., tens or hundreds of clock cycles). In this paper, we leverage a decision-tree-based power modeling approach to establish fine-grained hardware power monitoring on FPGA platforms. A generic and complete design flow is developed to implement the decision tree power model which is capable of precisely estimating dynamic power in a fine-grained manner. A flexible architecture of the hardware power monitoring is proposed, which can be instrumented in any RTL design for runtime power estimation, dispensing with the need for extra power measurement devices. Experimental results of applying the proposed model to benchmarks with different resource types reveal an average error up to 4% for dynamic power estimation. Moreover, the overheads of area, power and performance incurred by the power monitoring circuitry are extremely low. Finally, we apply our power monitoring technique to the power management using phase shedding with an on-chip multi-phase regulator as a proof of concept and the results demonstrate 14% efficiency enhancement for the power supply of the FPGA internal logic.

关键词： Decision trees Monitoring field programmable gate arrays Estimation Runtime Feature extraction Hardware

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Design of anti-reflective graded height nanogratings for photovoltaic applications 17

Design of anti-reflective graded height nanogratings for pho...

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17th international conference on Numerical Simulation of Optoelectronic Devices NUSOD

作者： Yasa, U. G. Erim, M. N. Erim, N. Girgin, M. O. Kurt, H. TOBB Univ Econ & Technol Dept Elect & Elect Engn Nanophoton Res Lab TR-06560 Ankara Turkey

ISBN: (纸本)9781509053230

Design of nanogratings with graded heights is proposed for solar-cell applications. the designed structure gives rise to absorption enhancement in solar-cells by reducing the reflection losses and focusing the incoming radiation into the photoactive layer. the results show that solar-cell efficiency is increased by 15% with graded height nanogratings.

关键词： Estimation field programmable gate arrays OFDM Modulation Filtration Clocks Signal processing algorithms

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A Fair and Comprehensive Large-Scale Analysis of Oscillation-Based PUFs for FPGAs 27

A Fair and Comprehensive Large-Scale Analysis of Oscillation...

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27th international conference on field programmable logic and applications (FPL)

作者： Wild, Alexander Becker, Georg T. Gueneysu, Tim NXP Semicond Eindhoven Netherlands ESMT Berlin Digital Soc Inst Berlin Germany Univ Bremen Bremen Germany

ISBN: (纸本)9789090304281

Physical Unclonable Functions (PUFs) have gained a lot of research attention in recent years resulting in many different PUF proposals. Several of these proposals were aimed specifically at FPGA implementations. However, often these PUFs are evaluated and implemented for different (and often old) FPGA families with different metrics. Missing implementation details in many papers further hamper a fair analysis, as small details such as the exact routing can have significant impact on the PUF performance. In this paper we aim to overcome these problems by providing a fair comparison of some of the most promising Weak PUFs for FPGAs, the classic Ring Oscillator PUF (RO PUF), the Loop PUF and the TERO PUF. Each PUF is implemented with the same area optimizations and careful manual routing for modern Xilinx Artix-7 FPGAs and several implementation options are discussed. We measure the reliability and uniqueness of the PUF constructs on 100 BASYS-3 boards for a temperature range of -22 degrees C to 44 degrees C and use a glitch-generating core to analyze the vulnerability of the PUF constructs to surrounding logic. Our results show that the RO PUF has the best reliability in the presence of temperature variations while TERO has the best uniqueness of the three considered PUFs. Interestingly, the TERO PUF also shows the highest resistance to surrounding logic. To encourage further research in FPGA PUFs and to enable a fair comparison to future work the implementations as well as the measurement data will be made publicly available.

关键词： Physical Unclonable Function (PUF) Ring Oscillator PUF TERO PUF Loop PUF field programmable Gate Array (FPGA)

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Reliable SEU Monitoring and Recovery using a programmable Configuration Controller 27

Reliable SEU Monitoring and Recovery using a Programmable Co...

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27th international conference on field programmable logic and applications (FPL)

作者： Gong, Lingkan Kroh, Alexander Agiakatsikas, Dimitris Nguyen, Nguyen T. H. Cetin, Ediz Diessel, Oliver UNSW Sydney Sch Comp Sci & Engn Sydney NSW Australia UNSW Sydney Sch Elect Engn & Telecommun Sydney NSW Australia Macquarie Univ Dept Engn N Ryde NSW Australia

ISBN: (纸本)9789090304281

FPGAs are promising candidates for computational tasks in space. However, they are susceptible to radiation-induced errors in their configuration memory. the recovery of configuration errors, either by device scrubbing or by module-based recovery, involves a series of reads and writes to the FPGA's configuration port, and is efficiently performed on-chip by a fast, flexible and reliable reconfiguration controller. In this work, we consider the reliability improvement of the recently proposed programmable Configuration Controller (PCC), a soft reconfiguration controller that has been shown to be both fast and flexible, but whose reliability, particularly in the face of radiation-induced configuration errors, has not until now been studied. To ensure that the PCC itself is reliable, we propose the use of traditional Triple Modular Redundant (TMR) combined with a novel software-based interrupt-driven fault recovery process that leverages hardware-accelerated configuration access. We report on our design space exploration to balance the utilization, error recovery performance, and reliability of the PCC. In extremely harsh radiation environments, the Mean Time to Failure of the PCC is as high as 25 years, compared with 3.5 hours for its non-protected counterpart, and that it takes as little as 27 ms to recover from a configuration memory error affecting the PCC.

关键词： field programmable gate arrays Tunneling magnetoresistance Synchronization Registers Reliability engineering Performance evaluation

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