检索结果-内蒙古大学图书馆

您好，读者！请登录

内蒙古大学图书馆

首页
概况
党建
资源
服务
科研支持
- 论文收录引用证明
- 科技查新
知识产权
档案馆
帮助

咨询与建议

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

您的常用邮箱：*

您的手机号码：*

问题描述：

当前已输入0个字，您还可以输入200个字

全部搜索
期刊论文
图书
学位论文
标准
纸本馆藏
外文资源发现
数据库导航
超星发现

高级检索

时间限定

出版年份：

文献类型

图书期刊文献学位论文多媒体

馆藏选择

电子馆藏纸本馆藏

核心期刊

全部期刊 SCI 收录期刊 SSCI 收录期刊 EI 收录期刊 CSCD 收录期刊 CSSCI 收录期刊

语言

中文英文

文献类型

期刊文献图书学位论文标准纸本馆藏

帮助

文字说明：

T=题名（书名、题名），A=作者（责任者），K=主题词，P=出版物名称，PU=出版社名称，O=机构（作者单位、学位授予单位、专利申请人），L=中图分类号，C=学科分类号，U=全部字段，Y=年（出版发行年、学位年度、标准发布年）

检索规则说明：

AND代表“并且”；OR代表“或者”；NOT代表“不包含”；(注意必须大写,运算符两边需空一格)

检索范例：

范例一：(K=图书馆学 OR K=情报学) AND A=范并思 AND Y=1982-2016
范例二：P=计算机应用与软件 AND (U=C++ OR U=Basic) NOT K=Visual AND Y=2011-2016

分类表

所选分类

>> <<

限定检索结果

文献类型

1,895 篇 会议
35 篇 期刊文献
4 册 图书

馆藏范围

1,934 篇 电子文献
0 种 纸本馆藏

日期分布

学科分类号

1,263 篇 工学
- 1,078 篇 计算机科学与技术...
- 724 篇 软件工程
- 423 篇 电气工程
- 192 篇 电子科学与技术（可...
- 69 篇 控制科学与工程
- 67 篇 信息与通信工程
- 25 篇 仪器科学与技术
- 25 篇 动力工程及工程热...
- 23 篇 建筑学
- 22 篇 机械工程
- 16 篇 生物工程
- 15 篇 土木工程
- 11 篇 核科学与技术
- 11 篇 生物医学工程（可授...
- 11 篇 安全科学与工程
- 10 篇 光学工程
- 7 篇 化学工程与技术
- 7 篇 交通运输工程
- 5 篇 农业工程
161 篇 理学
- 101 篇 数学
- 42 篇 物理学
- 19 篇 生物学
- 12 篇 系统科学
- 10 篇 统计学（可授理学、...
- 9 篇 化学
51 篇 管理学
- 39 篇 管理科学与工程(可...
- 17 篇 工商管理
- 15 篇 图书情报与档案管...
13 篇 法学
- 11 篇 社会学
9 篇 经济学
- 9 篇 应用经济学
6 篇 医学
5 篇 农学
4 篇 教育学
4 篇 军事学

主题

842 篇 field programmab...
694 篇 field programmab...
286 篇 hardware
156 篇 computer archite...
122 篇 logic gates
112 篇 table lookup
102 篇 clocks
86 篇 throughput
77 篇 routing
77 篇 random access me...
77 篇 acceleration
74 篇 software
68 篇 optimization
63 篇 kernel
62 篇 delays
53 篇 algorithm design...
52 篇 registers
52 篇 logic
51 篇 switches
45 篇 memory managemen...

机构

14 篇 univ toronto dep...
9 篇 brigham young un...
9 篇 imperial coll lo...
8 篇 department of co...
8 篇 ecole polytech f...
7 篇 univ british col...
7 篇 school of comput...
7 篇 imperial coll lo...
7 篇 tokyo inst techn...
6 篇 univ tsukuba tsu...
6 篇 university of ch...
6 篇 department of el...
6 篇 univ warwick sch...
6 篇 xilinx inc san j...
5 篇 univ manchester ...
5 篇 department of el...
5 篇 univ toronto dep...
5 篇 fudan univ state...
5 篇 swiss fed inst t...
5 篇 xilinx inc 2100 ...

作者

32 篇 luk wayne
21 篇 maruyama tsutomu
16 篇 koch dirk
13 篇 wayne luk
13 篇 wilton steven j....
12 篇 ienne paolo
11 篇 fahmy suhaib a.
11 篇 betz vaughn
10 篇 cheung peter y. ...
9 篇 vaughn betz
9 篇 constantinides g...
8 篇 prasanna viktor ...
8 篇 chow paul
8 篇 amano hideharu
8 篇 akash kumar
7 篇 kapre nachiket
7 篇 teich juergen
7 篇 suhaib a. fahmy
7 篇 alonso gustavo
7 篇 hutchings brad

语言

1,920 篇 英文
14 篇 其他

检索条件"任意字段=17th International Conference on Field Programmable Logic and Applications"

共 1934 条记录，以下是491-500 订阅

全选清除本页清除全部题录导出标记到"检索档案"

详细简洁

排序：

Find the Real Speed Limit: FPGA CAD for Chip-Specific Application Delay Measurement 27

Find the Real Speed Limit: FPGA CAD for Chip-Specific Applic...

引用

27th international conference on field programmable logic and applications (FPL)

作者： Ahmed, Ibrahim Zhao, Shuze Trescases, Olivier Betz, Vaughn Univ Toronto Dept Elect & Comp Engn Toronto ON Canada

ISBN: (纸本)9789090304281

Process variation is increasing with each successive technology node, and it has reached the point where the worst-case timing modelling employed by current FPGA CAD tools is significantly underutilizing the available silicon. Previous studies have proposed exploiting FPGA reconfigurability to reduce this underutilization using techniques such as late binding and dynamic voltage scaling. Most of the proposed solutions require the ability to measure the target application's delay on each configured chip. To accurately measure the delay of an application on a certain chip, we must measure the delay of its speed limiting paths on this specific chip. In this paper, we present a variation-aware CAD tool that automatically generates calibration bitstreams to measure the delay of any input application. Our tool identifies the statistically critical paths of the circuit and optimally selects which paths to test such that it minimizes the chances of reporting an optimistic delay, under a constraint on the number of allowed calibration bitstreams. Experimental results across a suite of benchmarks show that with one calibration bitstream we achieve 16x lower probability of reporting an optimistic delay compared to a greedy approach. With three calibration bitstreams, we reduce the probability of optimism to two chips in a million, approximately 6,000x lower than a greedy approach.

关键词： Delays Table lookup Calibration Semiconductor device measurement Integrated circuit modeling Computational modeling field programmable gate arrays

来源：评论

学校读者我要写书评

暂无评论

Modeling the Physical Properties of Two-Dimensional Nanomaterials 17

Modeling the Physical Properties of Two-Dimensional Nanomate...

引用

17th international conference on Numerical Simulation of Optoelectronic Devices NUSOD

作者： Voon, L. C. Lew Yan Univ West Georgia Coll Sci & Math Carrollton GA 30118 USA

ISBN: (纸本)9781509053230

In our presentation, I will review work done in enabling the development of two-dimensional nanomaterials for optoelectronic applications. the focus will be on the materials and the theories available for modeling them. I will start with a survey of the nanomaterials fabricated and predicted to exit, together with a discussion of their physical properties. this will be followed by a few examples of optoelectronic devices designed using these materials. Finally, we will present an overview of the theoretical tools developed to study electrons and phonons in these materials.

关键词： Estimation field programmable gate arrays OFDM Modulation Filtration Clocks Signal processing algorithms

来源：评论

学校读者我要写书评

暂无评论

Self-mode-locking in Quantum Dot unidirectional ring lasers: model and simulations 17

Self-mode-locking in Quantum Dot unidirectional ring lasers:...

引用

17th international conference on Numerical Simulation of Optoelectronic Devices NUSOD

作者： Columbo, Lorenzo Luigi Bardella, Paolo Montrosset, Ivo Gioannini, Mariangela Politecn Torino Dipartimento Elettron & Telecomunicaz Turin Italy

We predicted the occurrence of spontaneous mode-locking phenomena in Quantum Dot based unidirectional ring laser via Risken-Nummedal-Graham-Haken instability of the continuous wave emission. Very interestingly for app... 详细信息

ISBN: (纸本)9781509053230

关键词： Estimation field programmable gate arrays OFDM Modulation Filtration Clocks Signal processing algorithms

来源：评论

学校读者我要写书评

暂无评论

Accelerating In-System FPGA Debug of High-Level Synthesis Circuits using Incremental Compilation Techniques 27

Accelerating In-System FPGA Debug of High-Level Synthesis Ci...

引用

27th international conference on field programmable logic and applications (FPL)

作者： Bussa, Pavan Kumar Goeders, Jeffrey Wilton, Steven J. E. Univ British Columbia Dept Elect & Comp Engn Vancouver BC Canada Brigham Young Univ Dept Elect & Comp Engn Provo UT 84602 USA

ISBN: (纸本)9789090304281

High-Level Synthesis has emerged as a promising technology for improving FPGA designer productivity, but will only be successful if it is accompanied by a debug ecosystem. Recent efforts have presented in-system debug techniques which allow a designer to debug an implementation, running on an FPGA, in the context of the original source code. these techniques typically store a history of all user variables on chip. To maximize the effectiveness of the on-chip memory, it is desirable to store only selected user variables. Unfortunately, this may lead to multiple debug runs. In existing frameworks, changing the variables to be stored between runs requires a full recompile. In this paper, we propose several flows that use incremental compilation to reduce the debug turn-around time. the first flow, in which the user circuit and instrumentation are co-optimized during compilation, gives the fastest debug clock speeds but suffers in user circuit performance once the debug instrumentation is removed. In the second flow, the optimization of the user circuit is sacrosanct. It is placed and routed first without having any constraints and the debug instrumentation is added later leading to the fastest user circuit clock speeds, but performance suffers slightly during debug. Using either flow, we achieve 40% reduction in debug turn-around times, on average.

关键词： Instruments field programmable gate arrays Debugging History Tools Hardware System-on-chip

来源：评论

学校读者我要写书评

暂无评论

Scalable High-Performance Architecture for Convolutional Ternary Neural Networks on FPGA 27

Scalable High-Performance Architecture for Convolutional Ter...

引用

27th international conference on field programmable logic and applications (FPL)

作者： Prost-Boucle, Adrien Bourge, Alban Petrot, Frederic Alemdar, Hande Caldwell, Nicholas Leroy, Vincent Univ Grenoble Alpes CNRS Grenoble INP TIMAInst Engn F-38000 Grenoble France Univ Grenoble Alpes CNRS Grenoble INP LIGInst Engn F-38000 Grenoble France

ISBN: (纸本)9789090304281

thanks to their excellent performances on typical artificial intelligence problems, deep neural networks have drawn a lot of interest lately. However, this comes at the cost of large computational needs and high power consumption. Benefiting from high precision at acceptable hardware cost on these difficult problems is a challenge. To address it, we advocate the use of ternary neural networks (TNN) that, when properly trained, can reach results close to the state of the art using floating-point arithmetic. We present a highly versatile FPGA friendly architecture for TNN in which we can vary both the number of bits of the input data and the level of parallelism at synthesis time, allowing to trade throughput for hardware resources and power consumption. To demonstrate the efficiency of our proposal, we implement high-complexity convolutional neural networks on the Xilinx Virtex-7 VC709 FPGA board. While reaching a better accuracy than comparable designs, we can target either high throughput or low power. We measure a throughput up to 27000 fps at approximate to 7 W or up to 8.36 TMAC/s at approximate to 13 W.

关键词： Neurons Parallel processing Random access memory field programmable gate arrays Hardware throughput Neural networks

来源：评论

学校读者我要写书评

暂无评论

Bridging High-Level Synthesis and Application-Specific Arithmetic: the Case Study of Floating-Point Summations 27

Bridging High-Level Synthesis and Application-Specific Arith...

引用

27th international conference on field programmable logic and applications (FPL)

作者： Uguen, Yohann de Dinechin, Florent Derrien, Steven Univ Lyon INSA Lyon Inria CITI F-69621 Villeurbanne France Univ Rennes 1 IRISA Rennes France

ISBN: (纸本)9789090304281

FPGAs are well known for their ability to perform non-standard computations not supported by classical microprocessors. Many libraries of highly customizable application-specific IPs have exploited this capablity. However, using such IPs usually requires handcrafted HDL, hence significant design efforts. High Level Synthesis (HLS) lowers the design effort thanks to the use of C/C++ dialects for programming FPGAs. However, high-level C language becomes a hindrance when one wants to express non-standard computations: this languages was designed for programming microprocessors and carries with it many restrictions due to this paradigm. this is especially true when computing with floating-point, whose data-types and evaluation semantics are defined by the IEEE-754 and C11 standards. If the high-level specification was a computation on the reals, then HLS imposes a very restricted implementation space. this work attempts to bridge FPGA application-specific efficiency and HLS ease of use. It specifically targets the ubiquitous floating-point summation-reduction pattern. A source-to-source compiler transforms selected floating-point additions into sequences of simpler operators using non-standard arithmetic formats. this improves performance and accuracy for several benchmarks, while keeping the ease of use of a high-level C description.

关键词： field programmable gate arrays Hardware Tools Open area test sites Adders Program processors Optimization

来源：评论

学校读者我要写书评

暂无评论

Heterogeneous Virtualized Network Function Framework for the Data Center 27

Heterogeneous Virtualized Network Function Framework for the...

引用

27th international conference on field programmable logic and applications (FPL)

作者： Tarafdar, Naif Lin, thomas Eskandari, Nariman Lion, David Leon-Garcia, Alberto Chow, Paul Univ Toronto Toronto ON Canada

ISBN: (纸本)9789090304281

We present a framework for creating heterogeneous virtualized network function (VNF) service chains from cloud data center resources. Traditionally, these functions are packaged in software images within a catalog of networking applications that can be loaded onto a virtual machine CPU, and can be offered to users as a service. Our framework combines the best of both software and hardware by allowing users to chain traditional software-based VNFs with hardware-based VNFs that the user provides as an IP to generate a bitstream or a pre-generated VNF as part of a library. To accomplish this, our framework first creates the hardware bitstreams and programs the FPGA VNFs, loads any software VNFs requested, and programs the network to daisy chain the VNFs together. Furthermore, this enables an incremental design flow where the user can start by implementing a chain of VNFs in software and incrementally substitute software VNFs for their hardware counterparts. Our paper investigates two case studies to show the ability to switch between hardware and software VNFs in our framework and to demonstrate the benefit of using hardware VNFs. the first study is signature matching at fixed offsets, similar to matching packet headers. In this case study, the CPU can keep up at line-rate using specialized networking drivers. the second case study involves string matching within a packet, which requires scanning through the entire frame. In this case, the CPU performance drops to approximately 20 percent of the input rate, whereas the FPGA can continue to keep up at line-rate.

关键词： field programmable gate arrays Virtual machining Hardware Cloud computing IP networks

来源：评论

学校读者我要写书评

暂无评论

Customizing Low-Precision Deep Neural Networks for FPGAs

Customizing Low-Precision Deep Neural Networks for FPGAs

引用

international conference on field programmable logic and applications

作者： Julian Faraone Giulio Gambardella David Boland Nicholas Fraser Michaela Blott Philip H.W. Leong The University Of Sydney Xilinx Research Labs

ISBN: (数字)9781538685174

ISBN: (纸本)9781538685181

In this paper, we argue that instead of solely focusing on developing efficient architectures to accelerate well-known low-precision CNNs, we should also seek to modify the network to suit the FPGA. We develop a fully automative toolflow which focuses on modifying the network through filter pruning, such that it efficiently utilizes the FPGA hardware whilst satisfying a predefined accuracy threshold. Although fewer weights are re-moved in comparison to traditional pruning techniques designed for software implementations, the overall model complexity and feature map storage is greatly reduced. We implement the AlexNet and TinyYolo networks on the large-scale ImageNet and PascalVOC datasets, to demonstrate up to roughly 2× speedup in frames per second and 2× reduction in resource requirements over the original network, with equal or improved accuracy.

关键词： field programmable gate arrays Hardware Quantization (signal) throughput Memory management Neural networks

来源：评论

学校读者我要写书评

暂无评论

Differential Power Analysis of 8-Bit Datapath AES for IoT applications

Differential Power Analysis of 8-Bit Datapath AES for IoT Ap...

引用

IEEE international conference on Trust, Security and Privacy in Computing and Communications (TrustCom)

作者： Jiaming Xu Ao Fan Minyi Lu Weiwei Shan National ASIC System Engineering Research Center Southeast University Nanjing China

the security issue of Internet of things (IoT) applications causes wide concern nowadays. Lightweight encryption circuits are preferred in IoT due to its severe restrictions of chip area and power consumption, among which, 8-bit datapath Advanced Encryption Standard (AES) is popular for its mature algorithm, compact architecture and low power consumption. However, it is also subject to the side channel analysis (SCA) attack, which is rarely mentioned. In this paper, a novel differential power analysis (DPA) attack method specialized for 8-bit datapath AES is proposed, which exploits the correlation between the power consumption of S-Box and processed data. the method can traverse all the possibilities. As a result, it is effective for almost all the existing 8-bit AES architecture in theory. the first round of encryption is adopted as the target round, avoiding the complicated computing in AES algorithm to reduce the cost of attack and increase the success rate and efficiency. the effectivity of this kind of method is verified by FPGA implementation on SAKURA-G board, with a minimum of 3681 power traces to crack the correct sub-key.

关键词： Encryption Correlation Power demand Hardware Computer architecture field programmable gate arrays Hamming distance

来源：评论

学校读者我要写书评

暂无评论

Weather Forecast Support System Implemented into Robot Partner for Supporting Elderly People Using 17

Weather Forecast Support System Implemented into Robot Partn...

引用

Joint 17th World Congress of international-Fuzzy-Systems-Association / 9th international conference on Soft Computing and Intelligent Systems (IFSA-SCIS)

作者： Szeles, Julia Kubota, Naoyuki Woo, Jinseok Tokyo Metropolitan Univ Grad Sch Syst Design Tokyo Japan

ISBN: (纸本)9781509049172

this paper proposes a weather forecast system which has been implemented into a robot partner in order to support elderly people in their daily life. Using the current weather data, the weather condition, the wind speed and the temperature, the system provides different recommendation to the user by using Fuzzy logic. With the help of the system, the elderly people can organize their daily routine plans in a more convenient way by using the weather information which were received from the internet. the system advices the user to do activities related to the current weather condition. To decide the right recommendation pattern, we use Fuzzy logic to describe the rules. Depending on the current weather condition, temperature and the wind speed, the system is going to advice the user about what should he/she do. the discussed system is implemented into a robot partner but it can be also used as regular smartphone application too.

关键词： Estimation field programmable gate arrays OFDM Modulation Filtration Clocks Signal processing algorithms

来源：评论

学校读者我要写书评

暂无评论

没有更多数据了...

全选清除本页清除全部题录导出标记到“检索档案”

共194页 << < 46 47 48 49 50 51 52 53 54 55 > >>

检索报告对象比较合并检索0

隐藏清空

合并搜索

回到顶部

执行限定条件

内容：

评分：

请选择保存的检索档案：

请选择收藏分类：

订阅名称：

通借通还

温馨提示：

图书名称：

借书校区：

取书校区：

手机号码：

邮箱地址：

一卡通帐号：

电话和邮箱必须正确填写，我们会与您联系确认。

联系人：

所在院系：

联系邮箱：

联系电话：

内蒙古自治区呼和浩特市赛罕区大学西街235号邮编: 010021

建议与咨询 留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案： 新增检索档案 确定 取消

请选择收藏分类： 新增自定义分类 确定 取消

通借通还

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

请选择保存的检索档案：

请选择收藏分类：