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检索条件"任意字段=17th International Conference on Field Programmable Logic and Applications"

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Improve Performance of Machine Translation Service Using Memcached 17

Improve Performance of Machine Translation Service Using <i>...

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17th international conference on Computational Science and its applications (ICCSA)

作者： Gupta, Priyank Ahmad, Rashid Shrivastava, Manish Kumar, Pawan Sinha, Mukul K. Int Inst Informat Technol Language Technol Res Ctr Hyderabad 500032 Telangana India Expert Software Consultants Ltd Noida 201301 UP India

ISBN: (纸本)9781538638934

Sampark is machine translation system providing translations among nine pairs of Indian languages. Machine translation system is a class of natural language processing applications that is far more complex and highly compute intensive in nature. As the load on the deployed system increases, optimization becomes a challenge. Caching is one of the available options to improve the performance of a software system with increasing load which exhibit the characteristics of locality of reference. Sampark MT system being a natural language processing application exhibits this characteristic. Memcached is a well-known, simple, in-memory caching solution that has been applied to improve the performance of several distributed web applications in the past. this paper describes how memcached has been applied to improve the performance of Sampark machine translation service which is deployed on a large cluster of machines. By applying distributed caching to MT system the performance of the system has improved upto 40%.

关键词： Estimation field programmable gate arrays OFDM Modulation Filtration Clocks Signal processing algorithms

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Tile Size Selection for Optimized Memory Reuse in High-Level Synthesis 27

Tile Size Selection for Optimized Memory Reuse in High-Level...

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27th international conference on field programmable logic and applications (FPL)

作者： Liu, Junyi Wickerson, John Constantinides, George A. Imperial Coll London Dept Elect & Elect Engn London SW7 2AZ England

ISBN: (纸本)9789090304281

High-level synthesis (HLS) is well capable of generating control and computation circuits for FPGA accelerators, but still requires sufficient human effort to tackle the challenge of memory and communication bottlenecks. One important approach for improving data locality is to apply loop tiling on memory-intensive loops. Loop tiling is a well-known compiler technique that partitions the iteration space of a loop nest into chunks (or 'tiles') whose associated data can fit into size-constrained fast memory. the size of the tiles, which can significantly affect the memory requirement, is usually determined by partial enumeration. In this paper, we propose an analytical methodology to select a tile size for optimized memory reuse in HLS. A parametric polyhedral model is introduced to capture memory usage analytically for arbitrary tile sizes. To determine the tile size for data reuse in constrained on-chip memory, an algorithm is then developed to optimize over this model, using non-linear solvers to minimize communication overhead. Experimental results on three representative loops show that, compared to random enumeration with the same time budget, our proposed method can produce tile sizes that lead to a 75% average reduction in communication overhead. A case study with real hardware prototyping also demonstrates the benefits of using the proposed tile size selection.

关键词： System-on-chip Memory management field programmable gate arrays Arrays Silicon Random access memory Data models

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Toward a Pixel-Parallel Architecture for Graph Cuts Inference on FPGA 27

Toward a Pixel-Parallel Architecture for Graph Cuts Inferenc...

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27th international conference on field programmable logic and applications (FPL)

作者： Gao, Tianqi Choi, Jungwook Tsai, Shang-nien Rutenbar, Rob A. Univ Illinois Dept Elect & Comp Engn Champaign IL 61820 USA IBM TJ Waston Res Ctr Yorktown Hts NY USA WorldQuant LLC Old Greenwich CT USA Univ Pittsburgh Dept Comp Sci Pittsburgh PA 15260 USA Univ Pittsburgh Dept Elect & Comp Engn Pittsburgh PA 15260 USA

ISBN: (纸本)9789090304281

the method of Graph Cuts converts a Maximum a Posteriori (MAP) inference problem on a Markov Random field (MRF) into a network flow, which can be solved efficiently. Many computer vision problems can be conveniently cast as an inference task to find most likely labels for pixels. the method is widely used, but computationally burdensome. Prior accelerator attempts have failed to exploit the problem's attractive, maximum available parallelism: push-relabel flow solvers can run in parallel across every pixel. this paper describes the design and implementation of the first pixel-parallel Graph Cuts inference engine. Our prototype implements a 256-pixel tile of an image, implemented as 256 locally-connected pixel processors. A checkerboard scheduling scheme allows for maximum parallelism while avoiding critical data dependencies. A 150MHz implementation on an FPGA can solve a segmentation task in 6 microseconds. We also discuss strategies for extending our prototype to larger "virtual" images that span more than the physical extent of the inference tile. Our model suggests 2-40x speedups compared with previous accelerator experiments. To the best of our knowledge, this is the first fully functional, pixel-parallel accelerator demonstration for Graph Cuts inference.

关键词： Program processors Parallel processing field programmable gate arrays Prototypes Convergence Arrays

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Type-II Quantum Dot Nanowire Structures with Large Oscillator Strengths for Optical Quantum Gating applications 17

Type-II Quantum Dot Nanowire Structures with Large Oscillato...

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17th international conference on Numerical Simulation of Optoelectronic Devices NUSOD

作者： Taherkhani, Masoomeh Gregersen, Niels Willatzen, Morten Mork, Jesper Tech Univ Denmark Dept Photon Engn Orsteds Plads DK-2800 Lyngby Denmark

ISBN: (纸本)9781509053230

the exciton oscillator strength (OS) in type-II quantum dot (QD) nanowires is calculated by using a fast and efficient method. We propose a new structure in Double-Well QD (DWQD) nanowire that considerably increases OS of type-II QDs which is a key parameter in optical quantum gating in the stimulated Raman adiabatic passage (STIRAP) process [1] for implementing quantum gates.

关键词： Estimation field programmable gate arrays OFDM Modulation Filtration Clocks Signal processing algorithms

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High-Performance Video Content Recognition with Long-term Recurrent Convolutional Network for FPGA 27

High-Performance Video Content Recognition with Long-term Re...

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27th international conference on field programmable logic and applications (FPL)

作者： Zhang, Xiaofan Liu, Xinheng Ramachandran, Anand Zhuge, Chuanhao Tang, Shibin Ouyang, Peng Cheng, Zuofu Rupnow, Kyle Chen, Deming Univ Illinois Dept Elect & Comp Engn 1406 W Green St Urbana IL 61801 USA Tsinghua Univ Inst Microelect Beijing Peoples R China Beihang Univ Sch Elect & Informat Engn Beijing Peoples R China Inspirit IoT Inc Champaign IL USA

ISBN: (纸本)9789090304281

FPGA is a promising candidate for the acceleration of Deep Neural Networks (DNN) with improved latency and energy consumption compared to CPU and GPU-based implementations. DNNs use sequences of layers of regular computation that are well suited for HLS-based design for FPGA. However, optimizing large neural networks under resource constraints is still a key challenge. HLS must manage on-chip computation, buffering resources, and off-chip memory accesses to minimize the total latency. In this paper, we present a design framework for DNNs that uses highly configurable IPs for neural network layers together with a new design space exploration engine for Resource Allocation Management (REALM). We also carry out efficient memory subsystem design and fixed-point weight re-training to further improve our FPGA solution. We demonstrate our design framework on the Longterm Recurrent Convolution Network for video inputs. Our implementation on a Xilinx VC709 board achieves 3.1X speedup compared to an NVIDIA K80 and 4.75X speedup compared to an Intel Xeon with 17.5X lower energy per image.

关键词： IP networks field programmable gate arrays Resource management Optimization Neural networks Mathematical model Quantization (signal)

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Evaluating Irregular Memory Access on OpenCL FPGA Platforms: a Case Study with XSBench 27

Evaluating Irregular Memory Access on OpenCL FPGA Platforms:...

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27th international conference on field programmable logic and applications (FPL)

作者： Luo, Yingyi Wen, Xianshan Yoshii, Kazutomo Ogrenci-Memik, Seda Memik, Gokhan Finkel, Hal Cappello, Franck Northwestern Univ Dept Elect Engn & Comp Sci Evanston IL 60208 USA Argonne Natl Lab Math & Comp Sci Div Argonne IL 60439 USA Argonne Natl Lab Leadership Comp Facil Argonne IL 60439 USA

ISBN: (纸本)9789090304281

FPGAs are becoming an attractive choice as a heterogeneous computing unit for scientific computing because FPGA vendors are adding floating-point-optimized architectures to their product lines. Additionally, high-level synthesis (HLS) tools such as Altera OpenCL SDK are emerging, which could potentially break the FPGA programming wall and provide a streamlined flow for domain experts in scientific computing. On the other hand, providing high performance in the presence of irregular memory access patterns to off-chip memory remains a challenge for the automated synthesis flows. In this paper, we study the performance/energy characteristics of OpenCL-generated FPGA designs on irregular memory access patterns, targeting XSBench, a memory-intensive Monte Carlo simulation code, as a case study. To complete our study, we implement XSBench in OpenCL and study optimization strategies for FPGAs. We observe that our OpenCL implantation of XSBench achieves 50% higher energy efficiency on an Intel Arria10-based FPGA platform than that on an Intel Xeon 8-core CPU while trading off 35% of performance.

关键词： field programmable gate arrays Kernel Optimization Tools Hardware Digital signal processing Memory management

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Flexible FPGA design for FDTD using OpenCL 27

Flexible FPGA design for FDTD using OpenCL

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27th international conference on field programmable logic and applications (FPL)

作者： Kenter, Tobias Foerstner, Jens Plessl, Christian Paderborn Univ Paderborn Ctr Parallel Comp Warburger Str 100 D-33098 Paderborn Germany Paderborn Univ Dept Comp Sci Warburger Str 100 D-33098 Paderborn Germany Paderborn Univ Dept Elect Engn Warburger Str 100 D-33098 Paderborn Germany

ISBN: (纸本)9789090304281

Compared to classical HDL designs, generating FPGA with high-level synthesis from an OpenCL specification promises easier exploration of different design alternatives and, through ready-to-use infrastructure and common abstractions for host and memory interfaces, easier portability between different FPGA families. In this work, we evaluate the extent of this promise. To this end, we present a parameterized FDTD implementation for photonic microcavity simulations. Our design can trade-off different forms of parallelism and works for two independent OpenCL-based FPGA design flows. Hence, we can target FPGAs from different vendors and different FPGA families. We describe how we used pre-processor macros to achieve this flexibility and to work around different shortcomings of the current tools. Choosing the right design configurations, we are able to present two extremely competitive solutions for very different FPGA targets, reaching up to 172 GFLOPS sustained performance. With the portability and flexibility demonstrated, code developers not only avoid vendor lock-in, but can even make best use of real trade-offs between different architectures.

关键词： field programmable gate arrays Kernel Time-domain analysis Pipeline processing Finite difference methods Tools Pipelines

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Asynchronous Interface FIFO Design on FPGA for High-throughput NRZ Synchronisation 27

Asynchronous Interface FIFO Design on FPGA for High-throughp...

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27th international conference on field programmable logic and applications (FPL)

作者： Liu, Gengting Garside, James Furber, Steve Plana, Luis A. Koch, Dirk Univ Manchester Sch Comp Sci Manchester M13 9PL Lancs England

ISBN: (纸本)9789090304281

Networks-on-chip (NoCs) have become a new chip design paradigm as the size of transistors continues to shrink. Globally-asynchronous locally-synchronous (GALS) on-chip networks are proposed for solving issues such as large clock tree distribution and signal delay variations. More interestingly, for the GALS networks using m-of-n delay-insensitive interconnect, the asynchronous interconnect not only can be used for on-chip interconnection, but also provides a simple, direct and power-saving solution for off-chip interconnection. this paper presents an asynchronous interface FIFO design to improve throughput over asynchronous inter-chip links using 2-of-7 Non-Return-to-Zero (NRZ) encoding in an existing many-core system. the proposed design is suitable for implementation on commodity FPGAs without using the limited global clock buffer resources, but involves using the FPGA to implement asynchronous circuits. the interface FIFO is constructed from the transition detectors themselves rather than by employing a separate buffer in the more conventional fashion. the proposed solution has been demonstrated in an existing system and is suitable for adaptation to other asynchronous m-of-n NRZ coding protocols for high-throughput communication.

关键词： Detectors Image edge detection field programmable gate arrays Synchronization Optical signal processing Encoding

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FPGA Modeling Techniques for Detecting and Demodulating Multiple Wireless Protocols 27

FPGA Modeling Techniques for Detecting and Demodulating Mult...

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27th international conference on field programmable logic and applications (FPL)

作者： Drozdenko, Benjamin Handagala, Suranga Chowdhury, Kaushik Leeser, Miriam Louisiana Tech Univ Ruston LA 71270 USA Northeastern Univ ECE Dept Boston MA 02115 USA

ISBN: (纸本)9789090304281

In an increasingly interconnected world, the rising number of wireless devices in the Internet of things has caused heavy congestion on particular bandwidths (BWs). Due to spectrum scarcity, the need has arisen for these devices to operate on the same BWs. However, existing wireless devices are inflexible and have no capabilities to coexist with devices using other protocols. In this work, we propose new FPGA-based design techniques to receive multiple protocols on the same computing platform. Our methods incorporate tunable parameters, such as FIR filter length and number of bits per fixed-point word, to explore design tradeoffs regarding clock cycle, resource utilization, power consumption, and detection accuracy. We separate the physical (PHY) layer receive chains into a set of building blocks, including rate transition, pattern detection, and OFDM demodulation. We investigate implementation of the LTE physical downlink shared channel (PDSCH) and 802.11a protocols to test our techniques. LTE is the standard for high-speed wireless communication for mobile phones and data terminals;Wi-Fi uses variants of IEEE 802.11a. To ease the system development process, we develop our models using MathWorks Simulink, which supports auto-generation of HDL code for the non-critical sections and incorporation of handtuned HDL code as part of its black box interface. Our building blocks can be used by the wireless system modeling community to meet the needs of modern evolving wireless standards. In the future, our framework will allow researchers to achieve highperformance transceiver implementations on FPGA fabric for multiple cutting edge protocols.

关键词： Protocols field programmable gate arrays Long Term Evolution Wireless communication OFDM Clocks Demodulation

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In-Switch Approximate Processing: Delayed Tasks Management for MapReduce applications 27

In-Switch Approximate Processing: Delayed Tasks Management f...

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27th international conference on field programmable logic and applications (FPL)

作者： Mitsuzuka, Koya Hayashi, Ami Koibuchi, Michihiro Amano, Hideharu Matsutani, Hiroki Keio Univ Dept ICS Kohoku Ku 3-14-1 Hiyoshi Yokohama Kanagawa Japan Natl Inst Informat Chiyoda Ku 2-1-2 Hitotsubashi Tokyo Japan

ISBN: (纸本)9789090304281

In MapReduce, the parallel processing performance is often limited by only a few compute nodes that delay to complete given tasks. Although various techniques have been invented to handle such stragglers, these techniques mostly impose a burden on master node to monitor the progress of all the compute nodes, resulting in a new bottleneck as the number of compute nodes increases. As an alternative approach, in this paper, we propose to move such straggler management burden from master node to network switch that connects the master and compute nodes, because all the information goes through the switch. More specifically, the proposed network switch monitors output packets from Map tasks to detect stragglers. When detected, the proposed switch generates a response instead of the straggler based on the outputs of the other normal Map tasks, so that Reduce tasks can be started without delay. We introduce some approximate techniques for the proxy computation and response at the switch;thus our switch is called "ApproxSW." We implement ApproxSW on NetFPGA-SUME board that has four 10Gbit Ethernet (10GbE) interfaces and a Virtex-7 FPGA. An experiment shows that the ApproxSW functions do not degrade the original 10GbE switch performance. We also analyze the accuracy of the proxy computation and response for stragglers and show that the proposed approximation based on task similarity achieves the best accuracy.

关键词： Switches Monitoring Delays Pipeline processing Electronic mail

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