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Deception Planning Models for Cyber Security 17

Deception Planning Models for Cyber Security

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17th international conference on Computational Science and its applications (ICCSA)

作者： De Faveri, Cristiano Moreira, Ana Souza, Eric UNL FCT Dept Informat NOVA LINCS Caparica Portugal

ISBN: (纸本)9781538638934

Deception-based mechanisms are typically used to enhance overall security by causing misperception on adversaries who take actions in favor of defense. the process of creating deception is complex and demands careful planning to maximize the benefits while mitigating potential risks. Advances in creating deception planning processes for cyber security are generally based on military tactics, where deception has a long history. However, the complexity of computer systems demands deception planning processes that fit the needs of integrating deception into traditional software security mechanisms. this paper presents a survey of existing deception planning processes in military and digital realms. the goal of this review is to identify the scope of deception planning models, which tools have been used to plan deception, and how the planning is integrated into other activities in the software development phases. We identified 20 different features in the studies, which we used to compare them. the outcome of this survey can be used to facilitate the understanding of how deception planning has been conducted and supported while identifying potential gaps to be addressed in future research.

关键词： Estimation field programmable gate arrays OFDM Modulation Filtration Clocks Signal processing algorithms

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Preliminary study on an improved weight updating for fuzzy c-means with applications to image segmentation 17

Preliminary study on an improved weight updating for fuzzy c...

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Joint 17th World Congress of international-Fuzzy-Systems-Association / 9th international conference on Soft Computing and Intelligent Systems (IFSA-SCIS)

作者： Girish, Deeptha Singh, Vineeta Ralescu, Anca Univ Cincinnati EECS Dept Cincinnati OH 45220 USA

ISBN: (纸本)9781509049172

Fuzzy c-means is a popular clustering algorithm which allows a single data point to belong to more than one class at any given point. It has been used for a variety of applications especially when the applications are subjective and ambiguous. Image segmentation is one such application in which the decision of a certain pixel belonging to a particular cluster is very fuzzy. the weight associated with every data point is very important as it controls the decision of assigning the data point to a particular cluster. In this study, two novel methods of updating weights that take into account the goodness of clustering and spatial relationships are proposed in order to improve the results of clustering. Fuzzy c-means with our proposed method of updating weights is applied to different kinds of images to perform image segmentation.

关键词： Estimation field programmable gate arrays OFDM Modulation Filtration Clocks Signal processing algorithms

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An Automatic RTL Compiler for High-throughput FPGA Implementation of Diverse Deep Convolutional Neural Networks 27

An Automatic RTL Compiler for High-Throughput FPGA Implement...

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27th international conference on field programmable logic and applications (FPL)

作者： Ma, Yufei Cao, Yu Vrudhula, Sarma Seo, Jae-sun Arizona State Univ Sch Elect Comp & Energy Engn Tempe AZ 85287 USA Arizona State Univ Sch Comp Informat Decis Syst Engn Tempe AZ USA

ISBN: (纸本)9789090304281

Convolutional neural networks (CNNs) are rapidly evolving and being applied to a broad range of applications. Given a specific application, an increasing challenge is to search the appropriate CNN algorithm and efficiently map it to the target hardware. the FPGA-based accelerator has the advantage of reconfigurability and flexibility, and has achieved highperformance and low-power. Without a general compiler to automate the implementation, however, significant efforts and expertise are still required to customize the design for each CNN model. In this work, we present an RTL-level CNN compiler that automatically generates customized FPGA hardware for the inference tasks of various CNNs, in order to enable high-level fast prototyping of CNNs from software to FPGA and still keep the benefits of low-level hardware optimization. First, a generalpurpose library of RTL modules is developed to model different operations at each layer. the implementation of each module is optimized at the RTL level. Given a CNN algorithm, its structure is abstracted to a directed acyclic graph (DAG) and then complied with RTL modules in the library. the integration and dataflow of physical modules are predefined in the top-level system template and reconfigured during compilation. the runtime control of layer-by-layer sequential computation is managed by the proposed execution schedule so that even highly irregular and complex network topology, e.g. ResNet, can be compiled. the proposed methodology is demonstrated with end-to-end FPGA implementations of various CNN algorithms (e.g. NiN, VGG-16, ResNet-50, and ResNet-152) on two standalone Intel FPGAs, Stratix V and Arria 10. the performance and overhead of the automated compilation are evaluated. the compiled FPGA accelerators exhibit superior performance compared to state-ofthe- art automation-based works by >2x for various CNNs.

关键词： field programmable gate arrays (FPGA)

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Kiwi scientific acceleration at large: Incremental compilation and multi-FPGA HLS demo 27

Kiwi scientific acceleration at large: Incremental compilati...

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27th international conference on field programmable logic and applications, FPL 2017

作者： Greaves, David J. University of Cambridge Computer Laboratory United Kingdom

ISBN: (纸本)9789090304281

the Kiwi project revolves around a compiler that converts C#.NET bytecode into Verilog RTL and/or SystemC. An alpha version of the Kiwi toolchain is now open source and a user community is growing. We will demonstrate an incremental approach to large system assembly of HLS and blackbox components, based on an extended IP-XACT intermediate representation. We show how to address multi-FPGA designs with object passing between components, automatic configuration of shared memory maps and automatic assembly of debugging infrastructure. We will also demonstrate the use of the unsafe subset of the C# language for type casting between byte arrays and structures which is a common coding style for network protocol implementations. Unsafe programming is also needed for user-coded memory managers that need to essentially perform address arithmetic, but such procedures can commonly defeat the memory pool disambiguation algorithms in static analysis. © 2017 Ghent University.

关键词： field programmable gate arrays (FPGA)

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A Survey on FPGA Implementations in Embedded Augmented Reality applications

A Survey on FPGA Implementations in Embedded Augmented Reali...

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international conference on Wireless Networks and Embedded Systems (WECON)

作者： Amanpreet Kaur Chitkara University Institute of Engineering and Technology Chitkara University Punjab India

ISBN: (纸本)9781538670514

Since a long ago, most of the Augmented Reality (AR) applications are built using some general purpose devices such as computers and handhelds. In such general purpose devices, tasks are being processed using different softwares that make it difficult to obtain the real time results with high resolution and frame rate. there is a need to maintain a good performance but it invariably results into high cost of the overall project due to the requirement of higher clock frequency and high power. Mobility and processing power are the two basic requirements of an augmented reality application to provide an efficient immersion to the end user. An embedded architecture developed on field programmable Gate Array logic (FPGA) can supply both mobility and processing power to the AR applications. FPGA is a tiny chip that has the efficiency of hardware level executions. this paper gives a detailed account of FPGAs in AR applications in the field of computer vision & image processing, multimedia & computer graphics, communication and wearable computing.

关键词： field programmable gate arrays Real-time systems Augmented reality Hardware Image processing Task analysis

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Highly Efficient Superluminescent Light-Emitting Diodes (SLEDs) at 625-650 nm 17

Highly Efficient Superluminescent Light-Emitting Diodes (SLE...

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17th international conference on Numerical Simulation of Optoelectronic Devices NUSOD

作者： Matuschek, Nicolai Duelk, Marcus EXALOS AG Wagistr 21 CH-8952 Schlieren Switzerland

ISBN: (纸本)9781509053230

Superluminescent light-emitting diodes (SLEDs) are very attractive as compact, highly efficient light sources for various applications in the visible red spectral region. We simulate and discuss the electro-optical performance of SLEDs operating at center wavelengths of 625-650 nm. We show that for current SLED structures the optimum wavelength with respect to maximum luminous flux and power conversion efficiency is around 635 nm. Design improvements of the epitaxial layer structure offer the way to shorter wavelengths with higher luminous flux and efficiency values.

关键词： Estimation field programmable gate arrays OFDM Modulation Filtration Clocks Signal processing algorithms

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Metasurface: Multi-Element Optical System Design 17

Metasurface: Multi-Element Optical System Design

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17th international conference on Numerical Simulation of Optoelectronic Devices NUSOD

作者： Yilmaz, Nazmi Bagci, Fehim Taha Sumer, Can Demircioglu, Ibrahim Hakki Yilmaz, Burak Kurt, Hamza ASELSAN Inc Ankara Turkey TOBB Univ Econ & Technol Dept Elect & Elect Engn Ankara Turkey

ISBN: (纸本)9781509053230

Metasurfaces that control the amplitude, phase and polarization of light are two-dimensional ultra-thin optical components consisting of nanoscatterers. In this paper, we demonstrate a triplet zoom system by using three different planar lenses (metalenses) working at 600 nm. the movement of metalenses provide three f# values: 1, 1.25, 1.5 and three focal length values: 20, 25, 30 mu m, while total thickness does not change. Our design of triplet zoom system shows that zoom systems could be realized with metasurface applications.

关键词： Estimation field programmable gate arrays OFDM Modulation Filtration Clocks Signal processing algorithms

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Enabling Partial Reconfiguration and Low Latency Routing using Segmented FPGA NoCs 27

Enabling Partial Reconfiguration and Low Latency Routing usi...

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27th international conference on field programmable logic and applications (FPL)

作者： Vipin, Kizhepatt Gray, Jan Kapre, Nachiket Mahindra Ecole Cent Hyderabad Telangana India Gray Res LLC Bellevue WA USA Univ Waterloo Waterloo ON Canada

ISBN: (纸本)9789090304281

Deflection-routed FPGA overlay NoCs such as Hoplite suffer from high worst-case routing latencies due to the penalty of deflections at large system sizes. Segmentation of communication channels in such NoCs can (I) reduce worstcase packet routing latencies for FPGA traffic, (2) enable efficient composition of multi-application NoC workloads, and (3) ease the burden of supporting Partial Reconfiguration (PR) for FPGAs. We use segmentation of the NoC links by inserting isolation multiplexers along NoC links to split traffic into different regions. this segmentation reduces routing latencies by localizing the deflected packets to stay within the segmented region. this can be done either statically using configuration bits that can be changed per application phase approximate to 1000s of cycles or completely dynamically on a per-cycle basis based on packet addresses. For the Xilinx VC709 FPGA board, we build an 8x8 deflection-routed NoC, with 4x4 statically fracturable regions having 256b-wide links with 6% extra LUT resources and no extra pipelining cost to support fracturing while running at >200 MHz. We comprehensively outperform the CONNECT Torus NoC by 2-3x across various traffic patterns while using 4-7x less FPGA resources. When considering real-world traffic extracted from Sniper simulations of multi-processor PARSEC benchmarks, we observe up to 2.7x improvement in throughput for 8x8 NoC with static segmentation. With fully dynamic segmentation applied to large 30 x 7 NoC with 300b links, hosting a 1,680-core parallel processor, segmenting the NoC into six 5 x 7 segments uses an additional 1% of device LUTs but improves throughput by as much as 2.5 x for LOCAL traffic.

关键词： field programmable gate arrays Routing Multiplexing Switches Table lookup Fabrics Electronic mail

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Lite-CNN: A High-Performance Architecture to Execute CNNs in Low Density FPGAs

Lite-CNN: A High-Performance Architecture to Execute CNNs in...

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international conference on field programmable logic and applications

作者： Mário Véstias Rui Policarpo Duarte José T. de Sousa Horácio Neto INESC-ID ISEL Instituto Politecnico de Lisboa INESC-ID Universidade de Lisboa Portugal Inst. Super. Tecnico Universidade de Lisboa Lisboa Lisboa PT

ISBN: (数字)9781538685174

ISBN: (纸本)9781538685181

Due to the computational complexity of Convolutional Neural Networks (CNNs), high performance platforms are generally considered for their execution. However, CNNs are very useful in embedded systems and its execution right next to the source of data has many advantages, like avoiding the need for data communication. In this paper, we propose an architecture for CNN inference (Lite-CNN) that can achieve high performance in low density FPGAs. Lite-CNN adopts a fixed-point representation for both neurons and weights, which was already shown to be sufficient for most CNNs. Also, with a simple and known dot product reorganization, the number of multiplications is reduced to half. We show implementation results for 8 bit fixed-point in a ZYNQ7020 and extrapolate for other larger FPGAs. Lite-CNN achieves 410 GOPs in a ZYNQ7020.

关键词： Neurons Kernel field programmable gate arrays Convolution three-dimensional displays Computer architecture Mathematical model

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SPynq: Acceleration of Machine Learning applications over Spark on Pynq 17

SPynq: Acceleration of Machine Learning Applications over Sp...

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17th Annual international conference on Embedded Computer Systems - Architectures, Modeling, and Simulation (SAMOS)

作者： Kachris, Christoforos Koromilas, Elias Stamelos, Ioannis Soudris, Dimitrios NTUA Inst Commun & Comp Syst ICCS Athens Greece Natl Tech Univ Athens Dept Elect & Comp Engn Athens Greece

ISBN: (纸本)9781538634370

Spark is one of the most widely used frameworks for data analytics that offers fast development of applications like machine learning and graph computations in distributed systems. In this paper, we present SPynq: A framework for the efficient utilization of hardware accelerators over the Spark framework on heterogeneous MPSoC FPGAs, such as Zynq. Spark has been mapped to the Pynq platform and the proposed framework allows the seamlessly utilization of the programmable logic for the hardware acceleration of computational intensive Spark kernels. We have also developed the required libraries in Spark that hides the accelerator's details to minimize the design effort to utilize the accelerators. A cluster of 4 nodes (workers) based on the all-programmable MPSoCs has been implemented and the proposed platform is evaluated in a typical machine learning application based on logistic regression. the logistic regression kernel has been developed as an accelerator and incorporated to the Spark. the developed system is compared to a high-performance Xeon cluster that is typically used in cloud computing. the performance evaluation shows that the heterogeneous accelerator-based MpSoC can achieve up to 2.3x system speedup compared with a Xeon system (with 90% accuracy) and 20x better energy-efficiency. For embedded application, the proposed system can achieve up to 40x speedup compared to the software only implementation on low-power embedded processors and 30x lower energy consumption.

关键词： Sparks Hardware Program processors Libraries Machine learning field programmable gate arrays Cloud computing field programmable gate arrays Program processors sparks Cloud Computing Computer hardware Artificial Intelligence Machine Learning Libraries Accelerators design effort Performance Evaluation hardware accelerator

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