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检索条件"任意字段=17th International Conference on Field Programmable Logic and Applications"

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Algorithmic and memory optimizations on multiple application mapping onto FPGAs 17

Algorithmic and memory optimizations on multiple application...

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17th Annual international conference on Embedded Computer Systems - Architectures, Modeling, and Simulation (SAMOS)

作者： Sidiropoulos, Harry Koutras, Ioannis Soudris, Dimitrios Siozios, Kostas Natl Tech Univ Athens Sch Elect & Comp Engn Zografos Greece Aristotle Univ Thessaloniki Dept Phys Thessaloniki Greece

ISBN: (纸本)9781538634370

field programmable Gate Arrays (FPGAs) offer a low power flexible accelerator alternative due to their inherent parallelism. Reprogrammability, although its their key feature, it is used almost exclusively on design time due to the constrains imposed by the modern CAD tools that require even days to run and tens of GB of RAM. In order to effectively utilize FPGAs on run time we propose a novel methodology and the supporting toolflow that enable efficient mapping of multiple applications onto heterogeneous FPGAs. With the use of a floorplanning step, memory optimizations and custom memory allocators, we alleviate the constrains imposed by CAD tools, and provide a proof of concept that application mapping onto FPGAs can be done on run time. Experimental results prove the efficiency of the introduced solution, as we achieve application's mapping 40x faster on average compared to a state-of-art approach, without performance degradation and with 12x on average reduced memory usage.

关键词： field programmable gate arrays Tools Kernel Random access memory Memory management Optimization Hardware field programmable gate arrays random access machine Store management Computer hardware Mapping onto Runtime Kernel Memory Memory design year

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Xilinx FPGA Based Single Phase Five-Level Cascaded Z-Source Inverter

Xilinx FPGA Based Single Phase Five-Level Cascaded Z-Source ...

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India international conference on Power Electronics (IICPE)

作者： Jammy Ramesh Rahul A. Kirubakaran Department of Electrical Engineering National Institute of Technology Warangal Warangal

ISBN: (纸本)9781538649978;9781538649961

this paper presents a single phase five-level cascaded Z-source inverter with reduced number of switches for PV/FC/Wind power applications. the inherent benefits of z-source inverter are higher boost gain and fault ride through capability compared with the traditional VSI and CSI inverters. therefore five-level Z-source converter is simulated in MATLAB/Simulink environment and the generation of control pulses with the help of Xilinx System Generator is presented. A prototype model is developed to validate the theoretical concepts through experimental and simulation results.

关键词： Inverters field programmable gate arrays Matlab Mathematical model Generators Modulation logic gates

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Transport Properties of Nanostructured Graphene 17

Transport Properties of Nanostructured Graphene

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17th international conference on Numerical Simulation of Optoelectronic Devices NUSOD

作者： Jauho, Antti-Pekka Tech Univ Denmark DTU Nanotech CNG DK-2820 Lyngby Denmark

ISBN: (纸本)9781509053230

Despite of its many wonderful properties, pristine graphene has one major drawback: it does not have a band gap, which complicates its applications in electronic devices. Many routes have been suggested to overcome this difficulty, such as cutting graphene into nanoribbons, using chemical methods, or making regular nanoperforations, also known antidot lattices. theoretically, all these ideas lead to a reasonable band gap, but realizing them in the lab is very difficult because all fabrication steps induce disorder or other nonidealities, with potentially disasterous consequences for the intended device operation. In this talk I elaborate these ideas and review the state-of-the-art both from the theoretical and the experimental points of view. I also introduce two new ideas: (1) triangular antidots, and (2) nanobubbles formed in graphene. Both of these nanostructuring methods are predicted to yield novel transport signatures, which could form the basis of new types of devices. Our simulations show that it may be possible to generate very high quality spin- and/or valley polarized currents with these structures - something that has not yet been achieved in the lab. Importantly, our simulations involve millions of atoms which is necessary in order to address structures feasible in the lab.

关键词： Estimation field programmable gate arrays OFDM Modulation Filtration Clocks Signal processing algorithms

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Evaluation of the Shared-Memory Parallel Fast Marching Method for Re-Distancing Problems 17

Evaluation of the Shared-Memory Parallel Fast Marching Metho...

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17th international conference on Computational Science and its applications (ICCSA)

作者： Diamantopoulos, Georgios Weinbub, Josef Hossinger, Andreas Selberherr, Siegfried TU Wien Inst Microelect Christian Doppler Lab High Performance TCAD Vienna Austria Silvaco Europe Ltd St Ives England TU Wien Inst Microelect Vienna Austria

ISBN: (纸本)9781538638934

the Fast Marching Method is widely used for the solution of the Eikonal equation in problems arising in science and engineering applications. A common application is the calculation of the distance to an interface resulting in a signed distance field. the Fast Marching Method is a non-iterative high accuracy method. However, the sequential nature of the algorithm does not favor a straightforward parallelization. Many parallelization approaches have been presented so far, but they do not provide a reasonable parallel efficiency. Recently, a promising new approach based on an overlapping domain decomposition technique has been introduced, providing a scalable, widely applicable parallel algorithm. However, investigations so far were limited to synthetic point-based problem cases which do not cover the much more challenging cases of interface re-distancing, where instead of simplistic point sets, challenging interface geometries are processed. In this work we fill this gap by analyzing a shared-memory implementation of the parallel Fast Marching Method for three-dimensional interface problems, covering the key challenges and various domain decomposition strategies. the parallel efficiency and run-time performance is examined on a dual-socket Ivy Bridge-EP compute node. Our analyses clearly outline the feasibility limits of a shared-memory parallel Fast Marching Method.

关键词： Estimation field programmable gate arrays OFDM Modulation Filtration Clocks Signal processing algorithms

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New Results on Pre-aggregation Functions: introducing (light) pre-t-norms 17

New Results on Pre-aggregation Functions: introducing (light...

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Joint 17th World Congress of international-Fuzzy-Systems-Association / 9th international conference on Soft Computing and Intelligent Systems (IFSA-SCIS)

作者： Dimuro, Gracaliz P. Bustince, Humberto Fernandez, Javier Mesiar, Radko Bedregal, Benjamin UPNA ISC Pamplona Spain Fundacao Univ Fed Rio Grande C3 Rio Grande RS Brazil UPNA ISC DAC Pamplona Spain Slovak Univ Technol Bratislava DM Bratislava Slovakia Univ Fed Rio Grande do Norte DIMAP Natal RN Brazil

ISBN: (纸本)9781509049172

the aim of this paper is to enlarge the knowledge about the promising concept of a pre-aggregation function introduced by Lucca et al., which is a kind of "aggregation" concept that no longer requires monotonicity in all the function domain. For that, we introduce the notion of pre-t-norm, based on the important concept of t-norm. We also study the case of the so-called light pre-t-norms, which are particular non necessarily associative, commutative functions with neutral element e = 1, allowing for applications that do not require the associativity property, as it was extensively discussed in the literature. We analyse some properties of (light) pre-t-norms and the classes of (light) pre-t-norms, providing several examples.

关键词： Estimation field programmable gate arrays OFDM Modulation Filtration Clocks Signal processing algorithms

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Principal Component Analysis Approach in Selecting Type-1 and Type-2 Fuzzy Membership Functions for High-dimensional Data 17

Principal Component Analysis Approach in Selecting Type-1 an...

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Joint 17th World Congress of international-Fuzzy-Systems-Association / 9th international conference on Soft Computing and Intelligent Systems (IFSA-SCIS)

作者： Raj, Desh Gupta, Aditya Tanna, Kenil Garg, Bhuvnesh Rhee, Frank Chung-Hoon Indian Inst Technol Guwahati Dept Comp Sci & Engn Gauhati 781039 India Indian Inst Technol Guwahati Dept Math Gauhati 781039 India Hanyang Univ Dept Elect & Commun Engn Ansan 15588 South Korea

ISBN: (纸本)9781509049172

With increased interest in learning from data, algorithms that manipulate datasets containing hundreds of features have become popular in various fields such as medicine, image processing, geolocation, biochemistry, and computational linguistics. Since a number of these applications exploit the power of fuzzy sets in representing uncertainties, it may be considered essential to describe a method for selecting the most suitable fuzzy membership function to represent a high-dimensional dataset. In this paper, we propose such a method, which is based on dimensionality reduction using the Principal Component Analysis (PCA) technique, followed by the Wilcoxon Minimal Bin Size algorithm, which has earlier been evaluated on multidimensional datasets up to 8 dimensions. We further demonstrate our proposed method using two real datasets consisting of 281 and 500 features, respectively.

关键词： Estimation field programmable gate arrays OFDM Modulation Filtration Clocks Signal processing algorithms

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Deep Learning Challenges and Solutions with Xilinx FPGAs 17

Deep Learning Challenges and Solutions with Xilinx FPGAs

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IEEE/ACM 36th international conference on Computer-Aided Design (ICCAD)

作者： Delaye, Elliott Sirasao, Ashish Dudha, Chaithanya Das, Sabya Xilinx Inc San Jose CA 95124 USA

ISBN: (纸本)9781538630938

In this paper, we will describe the architectural, software, performance, and implementation challenges and solutions and current research on the use of programmable logic to enable deep learning applications. First a discussion of characteristics of building a deep learning system will described. Next architectural choices will be explained for how a FPGA fabric can efficiently solve deep learning tasks. Finally specific techniques for how DSPs, memories and are used in high performance applications will be described.

关键词： Machine learning field programmable gate arrays Quantization (signal) Arrays Acceleration Training

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SOCAO: Source-to-source OpenCL compiler for intel-altera FPGAS 4

SOCAO: Source-to-source OpenCL compiler for intel-altera FPG...

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international Workshop on FPGAs for Software Programmers, FSP 2017, co-located with international conference on field programmable logic and applications, FPL 2017

作者： Rohde, Johanna Martinez-Peiró, Marcos Gadea-Gironés, Rafael Computer Systems Group Technische Universität Darmstadt Germany Department of Electronic Engineering Universitat Politècnica de València Spain

ISBN: (纸本)9783800744435

this paper describes the SOCAO source-to-source compiler that allows transforming C/C++ code into an OpenCL accelerated program targeting Intel FPGA SDK for OpenCL. this drastically drops the requirements regarding the knowledge of the designers on parallel computing and hardware design, only C/C++ and the user-guide of the SOCAO compiler are now needed. Results show a 54% to 278% increase of speed for two well-known algorithms for cryptographic applications. the detailed description of the compiler, the user-guide and some outcomes of the project are also explained in this work. © VDE VERLAG GMBH ∙ Berlin ∙ Offenbach

关键词： field programmable gate arrays (FPGA)

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AutoRARE: An Automated Tool For Generating FPGA-Based Multi-Memory Hardware Accelerators For Compute-Intensive applications

AutoRARE: An Automated Tool For Generating FPGA-Based Multi-...

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IEEE international Performance Computing and Communications conference

作者： Shrikant S. Jadhav Clay Gloster Christopher Doss Youngsoo Kim Jannatun Naher Dept. of Electrical and Computer Engineering North Carolina A&T State University Greensboro NC Dept. of Computer Systems Technology North Carolina A&T State University Greensboro NC Dept. of Electrical and Computer Engineering Bradley University Peoria IL

ISBN: (纸本)9781538668092;9781538668085

In this paper, we present AutoRARE, a Java-based automated design tool for generating field programmable Gate Array (FPGA)-based hardware accelerators. AutoRARE automatically generates all VHDL models needed to build/synthesize a processor specifically tailored for each application. the user needs only provide the VHDL description of a special-purpose floating point Arithmetic logic Unit (ALU) or function core. the tool generates the VHDL description for the memory interface, memory controller, host processor interface, and the application specific processor. We also present details of the FPGA-based multi-memory hardware accelerator for accelerating computationally intensive applications, generated using AutoRARE. the multi-memory hardware accelerator is highly pipelined and able to simultaneously read and write multiple floating point values from multiple memories. the multi-memory architecture is the key to providing hardware accelerators that execute 10X-100X faster than typical multi-core processors. the Taylor Series expansion of the sine/cosine function is used as an application to demonstrate the merits of the multi-memory hardware accelerator. In our experiments, we executed the Taylor Series in software and compared execution times with an FPGA-based hardware implementation. Our experiments show that the FPGA-based multi-memory Taylor Series hardware accelerator is 481X faster than software executing the Taylor Series on a typical server.

关键词： Reconfigurable computing field-programmable gate arrays field-programmable custom computing machines High performance computing Multi-Memory architecture Multiple memory banks

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DESIGN AND IMPLEMENTATION OF programmable READ ONLY MEMORY USING REVERSIBLE DECODER ON FPGA 4

DESIGN AND IMPLEMENTATION OF PROGRAMMABLE READ ONLY MEMORY U...

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4th international conference on Signal Processing, Communication and Networking (ICSCN)

作者： Naguboina, Gopi Chand Anusudha, K. Pondicherry Univ Dept Elect Engn Pondicherry India

ISBN: (纸本)9781509047406

Reversible logic is the emerging field for research in present era. the aim of this paper is to design and synthesize a programmable Read Only Memory (PROM) using a reversible decoder which is designed using reversible logic with minimum quantum cost. the PROM is a programmable logic device which consists of fixed AND Gates and programmable OR gates array. Fixed AND gates can be termed as a decoder. PROM finds its applications in cell phones, RFID tags, video game consoles, medical devices, computers and other electronic devices. An n input and k output Boolean function f (a1, a2, a3,.., an) (referred as (n, k)) is said to be logically reversible if and only if, the number of inputs are equal to the number of outputs i.e., 'n' equals 'k' and the input pattern uniquely maps the output pattern. the reversible logic must run both forward and backward as well such that the inputs can also be retrieved from outputs. there are many reversible logic gates in literature like NOT gate, Feynman Gate (CNOT gate), Double Feynman Gate, Peres Gate, TR gate, Seynman Gate and many more. Fan-out and Feed-back are not allowed in logical Reversibility. To overcome the Fan out limitation, the signals from required output lines are duplicated to desired lines using additional reversible combinational circuits. Reversible logic owns its applications in various fields which include Quantum Computing, Optical Computing, Nano-technology, Computer Graphics, low power VLSI etc., Reversible logic is gaining its own importance in recent years largely due to its property of low power consumption and low heat dissipation. In this paper, the programmable Read Only Memory (PROM) using reversible decoder which has less heat dissipation and low power consumption is proposed. the designed circuit is analyzed in terms of quantum cost, garbage outputs and number of gates. the Circuit has been designed and simulated using Xilinx software and implemented on FPGA SPARTAN - 3E.

关键词： PROM PLDS Quantum Cost Reversible Gates Garbage Outputs Number of gates

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