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RSVP: Soft Error Resilient Power Savings at Near-threshold Voltage using Register Vulnerability 47

RSVP: Soft Error Resilient Power Savings at Near-Threshold V...

引用

47th IEEE/IFIP Annual international conference on Dependable Systems and Networks (DSN)

作者： Tan, Li DeBardeleben, Nathan Guan, Qiang Blanchard, Sean Lang, Michael Los Alamos Natl Lab Ultrascale Syst Res Ctr Los Alamos NM 87545 USA

ISBN: (纸本)9781538622728

With the ever-growing scaling of computing capability, computing systems like supercomputers and embedded systems are bounded by limited power nowadays. Upon the mutually constrained nature between power efficiency and resilience, trade-offs of them have been extensively studied for achieving the optimal performance-power ratio, either under a certain power cap, or within the requirement of quality metrics of applications. theoretically, running programs in the low-power mode of computational components (e.g., CPU/GPU) can lead to increasing on-chip failure rates in terms of register-level susceptibility to soft errors. However, experimentally, such errors may not arise due to register vulnerability - errors occur at non-vulnerable register access intervals are invalidated and thus will not propagate to later execution. In this work, leveraging register vulnerability, we investigate the validity of failure rates in computing systems at Near-threshold Voltage (NTV), and empirically evaluate the practice of achieving optimal power savings without incurring observable number of soft errors during program runs. We propose the framework of RegiSter Vulnerability based Power efficiency (RSVP) for reliable and power efficient computing. Experimental results for a wide spectrum of applications on a power-aware simulated platform demonstrate the power saving capability of RSVP, by 11.2% on average, without incurring runtime soft errors at the optimal NTV level for power savings.

关键词： Estimation field programmable gate arrays OFDM Modulation Filtration Clocks Signal processing algorithms

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One size does not fit all: Implementation trade-offs for iterative stencil computations on FPGAs

One size does not fit all: Implementation trade-offs for ite...

引用

international conference on field programmable logic and applications

作者： Gaël Deest Tomofumi Yuki Sanjay Rajopadhye Steven Derrien Univ. Rennes 1 / IRISA INRIA / IRISA Colorado State University

Iterative stencils are kernels in various application domains such as numerical simulations and medical imaging, that merit FPGA acceleration. the best architecture depends on many factors such as the target platform, off-chip memory bandwidth, problem size, and performance requirements. We generate a family of FPGA stencil accelerators targeting emerging System on Chip platforms, (e.g., Xilinx Zynq or Intel SoC). Our designs come with design knobs to explore trade-offs. We also propose performance models to hone in on the most interesting design points, and show how they accurately lead to optimal designs. the optimal choice depends on problem sizes and performance goals.

关键词： field programmable gate arrays System-on-chip Pipeline processing Memory management Acceleration Bandwidth Hardware

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the Monte Carlo PUF

The Monte Carlo PUF

引用

international conference on field programmable logic and applications

作者： Vladimir Rožić Bohan Yang Jo Vliegen Nele Mentens Ingrid Verbauwhede COSIC KU Leuven Leuven-Heverlee Belgium Katholieke Universiteit Leuven Leuven Flanders BE

Physically unclonable functions are used for IP protection, hardware authentication and supply chain security. While many PUF constructions have been put forward in the past decade, only few of them are applicable to FPGA platforms. Strict constraints on the placement and routing are the main disadvantages of the existing PUFs on FPGAs, because they place a high effort on the designer. In this paper we propose a new delay-based PUF construction called Monte Carlo PUF, that does not require low-level placement and routing control. this construction relies on the on-chip Monte Carlo method that is applied for measuring the delays of logic elements in order to extract a unique device fingerprint. the proposed construction allows a trade-off between the evaluation time and the error rate. the Monte Carlo PUF is implemented and evaluated on Xilinx Spartan-6 FPGAs.

关键词： Monte Carlo methods Delays field programmable gate arrays Delay lines Radiation detectors Ring oscillators Security

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Generic and universal parallel matrix summation with a flexible compression goal for Xilinx FPGAs

Generic and universal parallel matrix summation with a flexi...

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international conference on field programmable logic and applications

作者： thomas B. Preußer Technische Universitat Dresden Dresden Sachsen DE

Bit matrix compression is a highly relevant operation in computer arithmetic. Essentially being a multi-operand addition, it is the key operation behind fast multiplication and many higher-level operations such as multiply-accumulate, the computation of the dot product or the implementation of FIR filters. Compressor implementations have been constantly evolving for greater efficiency both in general and in the context of concrete applications or specific implementation technologies. this paper is building on this history and describes a generic implementation of a bit matrix compressor for Xilinx FPGAs, which does not require a generator tool. It contributes FPGA-oriented metrics for the evaluation of elementary parallel bit counters, a systematic analysis and partial decomposition of previously proposed counters and a fully implemented construction heuristic with a flexible compression target matching the device capabilities. the generic implementation is agnostic of the aspect ratio of the input matrix and can be used for multiplication the same way as it can be for single-column population count operations.

关键词： Radiation detectors Table lookup Adders field programmable gate arrays Measurement Sociology Statistics

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Line rate programmable packet processing in 100Gb networks

Line rate programmable packet processing in 100Gb networks

引用

international conference on field programmable logic and applications

作者： Pavel Benáček Viktor Puš Jan Kořenek Michal Kekely CESNET Prague6 Czech Republic Netcope Technologies Sochorova Brno Czech Republic

the P4 language provides a way to describe a custom network packet processing behavior that involves header parsing, matching and assembling modified packets. Such abstraction represents a significant step towards removing the limitation of fixed-function networking devices. Our live demonstration shows a straightforward usage of an algorithm and tool that maps a P4 program to a general architecture of FPGA-based networking device. Network traffic is received, parsed, filtered and modified by the generated circuit at the full line rate of 100 Gbps Ethernet. the results of our ongoing joint research project NFV200 show that the FPGA technology can be used to improve network flexibility without the usual burden of tedious and error-prone HDL coding.

关键词： field programmable gate arrays Protocols Pipeline processing Standards Software Tools Hardware design languages

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A dynamic partial reconfigurable overlay concept for PYNQ

A dynamic partial reconfigurable overlay concept for PYNQ

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international conference on field programmable logic and applications

作者： Benedikt Janßen Pascal Zimprich Michael Hübner Ruhr-Universitat Bochum Bochum Nordrhein-Westfalen DE Embedded Systems for Information Technology Ruhr-University Bochum Bochum Germany

Partial reconfiguration is a promising technique in the design of embedded systems since it enables an increase in efficiency and flexibility. However, its usage is still challenging due to the constraints of current FPGAs. In this paper, we present an extension of the Xilinx Python package `pynq' to ease the usage of partial reconfigurable bitstreams. the pynq package belongs to Xilinx's open source project PYNQ. the PYNQ project provides the Python language and its libraries to developers on the Xilinx Zynq. Our pynq package extension enables the usage of partial reconfigurable bitstreams. the concept is based on our Python package `pynqpartial'. this package can be integrated into an overlay for PYNQ to enable support for partial reconfigurable bitstreams. Our goal is to enable overlay developers to offer overlays which manage the partial reconfiguration transparent to the Python programmer. We evaluated our approach on the PYNQ-Z1.

关键词： Software field programmable gate arrays Tools Dictionaries Computer architecture Programming

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Exploration of OpenCL for FPGAs using SDAccel and comparison to GPUs and multicore CPUs

Exploration of OpenCL for FPGAs using SDAccel and comparison...

引用

international conference on field programmable logic and applications

作者： Lester Kalms Diana Göhringer Technische Universität Dresden Dresden Germany

Due to energy efficiency, heterogeneous computing is gaining more and more attention. Since FPGA implementations are time consuming, high-level synthesis (HLS) is used to close the productivity gap. OpenCL has become accepted as a good programming model for HLS, due to its portability, good capability of design verification and rich instruction set. this work implements different optimization strategies using OpenCL for a heterogeneous system containing CPU, integrated GPU, GPU and FPGA. Energy efficiency and performance of the architectures are compared using a feature detection algorithm. It is shown how to maximize performance while hitting the maximum memory bandwidth and keeping the resource utilization low for the SDAccel tool from Xilinx. the evaluation shows the great streaming capability of OpenCL for FPGAs. the FPGA achieves a speed up of 62.8 and consumes 49 times less energy for the application in comparison to an optimized single threaded CPU implementation in full HD.

关键词： Kernel field programmable gate arrays Graphics processing units Bandwidth Optimization Resource management

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Functional & timing in-hardware verification of FPGA-based designs using unit testing frameworks

Functional & timing in-hardware verification of FPGA-based d...

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international conference on field programmable logic and applications

作者： Julian Caba Fernando Rincoon Julio Daniel Dondo Department of Technology and Information Systems University of Castilla-La Mancha Spain Universidad de Castilla-La Mancha Ciudad Real Castilla-La Mancha ES

In this PhD dissertation, we propose a new testing approach for effectively managing hardware development risks, producing hardware designs with enough quality and reliability. Our proposal is based on the combination of high-level modelling and a unit testing framework in order to generate real hardware implementations for validating the designer intent, in order to keep a high cycle-accuracy and a low design effort. Such real hardware implementations are based on FPGAs, whose reconfigurability are key to provide a flexible verification environment, whereas unit testing frameworks have been extended to consider new testing requirements beyond pure functionality, such as timing analysis. Moreover, we provide a hardware library with two different types of components: 1) monitors to check internal variables at run time, keeping the errors to later trace them, and 2) double functions to reduce third-party dependencies.

关键词： Hardware Testing Timing field programmable gate arrays Tools Proposals Biological system modeling

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Two-LUT-based synthesizable temperature sensor for Virtex-6 FPGA devices

Two-LUT-based synthesizable temperature sensor for Virtex-6 ...

引用

international conference on field programmable logic and applications

作者： Stephan Nolting Lin Liu Guillermo Payá-Vayá Institute of Microelectronic Systems Leibniz Universitä t Hannover Hannover Germany

this paper proposes a new synthesizable oscillator-based temperature sensor with minimal footprint for use in contemporary Xilinx FPGA devices. In contrast to previously published ring-oscillator architectures, based on inverters mapped onto single LUTs, the proposed oscillator uses an asynchronous Gray-coded 4-bit counter requiring only two 6-input LUTs. Due to its reduced hardware requirements, the feedback path can be implemented using local routing signals only. therefore, the impact of the routing on the oscillator frequency is slightly reduced making the oscillator less prone to placement-caused routing deviations. the proposed temperature sensor is calibrated using a two-point calibration approach, resulting in a mean accuracy of ±0.71° C with a mean resolution of 0.0081° C. As a further case study, a methodology to characterize on-chip semiconductor variations between identical FPGAs and within the same FPGA chip is presented using a sensor array, including up to 196 of the proposed two-LUT-based oscillators.

关键词： Oscillators Temperature sensors field programmable gate arrays Routing Table lookup Temperature measurement Radiation detectors

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Parallel dot-products for deep learning on FPGA

Parallel dot-products for deep learning on FPGA

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international conference on field programmable logic and applications

作者： Mário Véstias Rui Policarpo Duarte José T. de Sousa Horácio Neto INESC-ID Instituto Politécnico de Lisboa INESC-ID Universidade de Lisboa Portugal

Deep neural networks have recently shown great results in a vast set of image applications. the associated deep learning models are computationally very demanding and, therefore, several hardware solutions have been proposed to accelerate their computation. FPGAs have recently shown very good performances for these kind of applications and so it is considered a promising platform to accelerate the execution of deep learning algorithms. A common operation in these algorithms is multiply-accumulate (MACC) that is used to calculate dot-products. Since many dot products can be calculated in parallel, as long as memory bandwidth is available, it is very important to implement this operation very efficiently to increase the density of MACC units in an FPGA. In this paper, we propose an implementation of parallel MACC units in FPGA for dot-product operations with very high performance/area ratios using a mix of DSP blocks and LUTs. We consider fixed-point representations with 8 bits of size, but the method can be applied to other bit widths. the method allows us to achieve TOPs performances, even for low cost FPGAs.

关键词： Digital signal processing Table lookup field programmable gate arrays Adders Machine learning Lead Bandwidth

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