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Dynamic power estimation based on switching activity propagation

Dynamic power estimation based on switching activity propaga...

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international conference on field programmable logic and applications

作者： Y. Nasser J.-C. Prévotet Maryline Hélard J. Lorandel Institut national des sciences appliquées de Rennes INSA Rennes - IETR Rennes France ETIS CNRS Cergy-Pontoise France

A new power estimation approach based on the decomposition of a digital system into basic operators is presented. this approach aims to estimate the energy consumption at early design phases of digital blocks implemented on FPGAs. Each operator has its own model which estimates the switching activity and the power consumption. By interconnecting several operators, statistical information is then propagated to provide a global power estimation of a given system. A simple sum of the power dissipation contribution of each operator is enough to compute the total power consumption. this is performed by taking into account the switching activities relative to a given input pattern. Earlier, faster and more flexible power analysis for system designers are the advantages. this approach has been evaluated in a use-case application. the preliminary results indicate a promising speed-up of the design process and an error which is less than 8.0% compare to the classical power estimation tools.

关键词： Estimation Integrated circuit modeling field programmable gate arrays Switches Computational modeling Power demand Neural networks

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Parallel RRT∗ architecture design for motion planning

Parallel RRT∗ architecture design for motion planning

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international conference on field programmable logic and applications

作者： Size Xiao Neil Bergmann Adam Postula School of Information Technology and Electrical Engineering The University of Queensland QLD Australia University of Queensland Brisbane QLD AU

A motion planning algorithm aims to calculate one obstacle-free trajectory which meets the dynamical constraints of a vehicle and leads the vehicle from the start state to the target state. RRT* (RRT star) is one sampling-based algorithm which is widely used in many applications because of its speed in quickly finding a trajectory. In contrast with basic RRT (Rapidly-exploring Random Trees) algorithm, RRT* improves trajectory optimality significantly by introducing the refinement step after setting up each tree node. this paper describes a new parallel version of the RRT* algorithm and its corresponding architecture on an FPGA (field programmable Gate Arrays). the refinement step is extracted and runs as a parallel process alongside a continuous tree-extending process. In order to avoid traversing all nodes in every iteration, tree nodes are stored in separate memory blocks and each block is assigned its own tree extending and refining pipelines to enhance the memory throughput. In the experimental evaluation, we take a 3-dimensional state spaces and implement the proposed architecture. the hardware implementation gives a 90 times speed improvement compared with an embedded software implementation, and a 30 times speedup compared to a desktop software implementation.

关键词： Computer architecture Pipelines Random access memory Algorithm design and analysis field programmable gate arrays Refining Planning

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doppioDB: A hardware accelerated database

doppioDB: A hardware accelerated database

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international conference on field programmable logic and applications

作者： David Sidler Muhsen Owaida Zsolt István Kaan Kara Gustavo Alonso Systems Group ETH Zürich

Relational databases provide a wealth of functionality to a wide range of applications. Yet, there are tasks for which they are less than optimal, for instance when processing becomes more complex (e.g., regular expression evaluation, data analytics) or the data is less structured (e.g., text or long strings). With the increasing amount of user-generated data stored in relational databases, there is a growing need to analyze unstructured text data. At the same time more complex analytical operators are required to extract useful information from the vast amount of collected data. However, many analytical operators incur a significant compute complexity not suitable to database engines where multiple queries share the available resources. In this demonstration we show the benefit of using specialized hardware for such tasks and highlight the importance of a flexible, reusable mechanism for extending database engines with hardware-based operators. Our hybrid database engine, doppioDB, is deployed on an emerging Xeon+FPGA multicore architecture where the CPU and FPGA have cache-coherent access to the same memory, such that the hardware operators can directly access the database tables. the demonstration is illustrating the acceleration benefits of hardware operators, as well as doppioDB's flexibility in accommodating changing workloads.

关键词： Hardware Acceleration Databases field programmable gate arrays Engines Software

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Flexible FPGA design for FDTD using OpenCL

Flexible FPGA design for FDTD using OpenCL

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international conference on field programmable logic and applications

作者： Tobias Kenter Jens Förstner Christian Plessl Department of Computer Science Paderborn Center for Parallel Computing Department of Electrical Engineering Paderborn University Paderborn Germany

Compared to classical HDL designs, generating FPGA with high-level synthesis from an OpenCL specification promises easier exploration of different design alternatives and, through ready-to-use infrastructure and common abstractions for host and memory interfaces, easier portability between different FPGA families. In this work, we evaluate the extent of this promise. To this end, we present a parameterized FDTD implementation for photonic microcavity simulations. Our design can trade-off different forms of parallelism and works for two independent OpenCL-based FPGA design flows. Hence, we can target FPGAs from different vendors and different FPGA families. We describe how we used pre-processor macros to achieve this flexibility and to work around different shortcomings of the current tools. Choosing the right design configurations, we are able to present two extremely competitive solutions for very different FPGA targets, reaching up to 172 GFLOPS sustained performance. With the portability and flexibility demonstrated, code developers not only avoid vendor lock-in, but can even make best use of real trade-offs between different architectures.

关键词： field programmable gate arrays Kernel Time-domain analysis Pipeline processing Finite difference methods Tools Pipelines

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A fair and comprehensive large-scale analysis of oscillation-based PUFs for FPGAs

A fair and comprehensive large-scale analysis of oscillation...

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international conference on field programmable logic and applications

作者： Alexander Wild Georg T. Becker Tim Güneysu NXP semiconductors Digital Society Institute Berlin University of Bremen

Physical Unclonable Functions (PUFs) have gained a lot of research attention in recent years resulting in many different PUF proposals. Several of these proposals were aimed specifically at FPGA implementations. However, often these PUFs are evaluated and implemented for different (and often old) FPGA families with different metrics. Missing implementation details in many papers further hamper a fair analysis, as small details such as the exact routing can have significant impact on the PUF performance. In this paper we aim to overcome these problems by providing a fair comparison of some of the most promising Weak PUFs for FPGAs, the classic Ring Oscillator PUF (RO PUF), the Loop PUF and the TERO PUF. Each PUF is implemented with the same area optimizations and careful manual routing for modern Xilinx Artix-7 FPGAs and several implementation options are discussed. We measure the reliability and uniqueness of the PUF constructs on 100 BASYS-3 boards for a temperature range of -22°C to 44°C and use a glitch-generating core to analyze the vulnerability of the PUF constructs to surrounding logic. Our results show that the RO PUF has the best reliability in the presence of temperature variations while TERO has the best uniqueness of the three considered PUFs. Interestingly, the TERO PUF also shows the highest resistance to surrounding logic. To encourage further research in FPGA PUFs and to enable a fair comparison to future work the implementations as well as the measurement data will be made publicly available.

关键词： field programmable gate arrays Radiation detectors Delays Layout Table lookup Oscillators Frequency measurement

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A Runtime Reconfigurable FPGA-Based Microphone Array for Sound Source Localization 26

A Runtime Reconfigurable FPGA-Based Microphone Array for Sou...

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26th international conference on field-programmable logic and applications (FPL)

作者： da Silva, Bruno Segers, Laurent Braeken, An Touhafi, Abdellah VUB Dept INDI Brussels Belgium

ISBN: (纸本)9782839918442

Microphone arrays are able to recognize, profile and locate sound-sources in noisy environments, but their quality is determined by the number of microphones. A higher number of microphones increases the computational demand, making real-time response challenging. In this demo, we present a scalable and runtime reconfigurable architecture able to support a variable number of microphones and orientations in order to provide accurate sound-source localization in real-time.

关键词： field programmable gate arrays (FPGA)

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Development of fully FPGA-based 3D (X, Y, t) detection systems using multi-channel Tapped-Delay-Line Time-to-Digital Converter with Cross Delay-Line detectors

Development of fully FPGA-based 3D (X, Y, t) detection syste...

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IEEE Nuclear Science Symposium and Medical Imaging conference (NSS/MIC) / 24th international Symposium on Room-Temperature Semiconductor X-Ray and Gamma-Ray Detectors

作者： Lusardi, N. Garzetti, F. Geraci, A. Cautero, G. Dri, C. Pittana, P. Sergo, R. Stebel, L. Politecn Milan DEIB Via Golgi 40 I-20133 Milan MI Italy Elettra Sincrotrone Trieste SS 14Km 1635 AREA Sci Pk I-34149 Trieste Italy

ISBN: (纸本)9781538622827

Time-resolved experiments often need detection devices able to provide information about position and arrival time of each detected event. Time resolution is a fundamental requirement for these devices, along with the high versatility and fast real-time computing of the acquisition system. Typical architectures, based on Time-to-Digital Converters (TDC) followed by a FPGA, combine very fast parallel computing with a time precision better than hundreds of picoseconds, allowing to perform state-of-the-art time-resolved experiments. Nevertheless, time resolution is still a limiting factor, in particular for imaging applications where the detector spatial resolution is determined through time measurement. Furthermore, the separation between the TDC devices and a readout FPGA has some drawbacks in terms of versatility of the system. In this article, we present a new approach, combining FPGA-based multi-channel Tapped-Delay-Line TDC and an efficient multipurpose readout logic, to greatly improve the overall performance and versatility of Cross Delay-Line (CDL) detector systems.

关键词： Detectors field programmable gate arrays Time measurement Channel estimation Spatial resolution Synchrotrons Probes

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Scalable high-performance architecture for convolutional ternary neural networks on FPGA

Scalable high-performance architecture for convolutional ter...

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international conference on field programmable logic and applications

作者： Adrien Prost-Boucle Alban Bourge Frédéric Pétrot Hande Alemdar Nicholas Caldwell Vincent Leroy TIMA Grenoble Institute of Engineering Univ. Grenoble Alpes Grenoble France Institut NEEL Grenoble RhÃ´ne-Alpes FR CNRS Grenoble Institute of Engineering Univ. Grenoble Alpes

thanks to their excellent performances on typical artificial intelligence problems, deep neural networks have drawn a lot of interest lately. However, this comes at the cost of large computational needs and high power consumption. Benefiting from high precision at acceptable hardware cost on these difficult problems is a challenge. To address it, we advocate the use of ternary neural networks (TNN) that, when properly trained, can reach results close to the state of the art using floatingpoint arithmetic. We present a highly versatile FPGA friendly architecture for TNN in which we can vary both the number of bits of the input data and the level of parallelism at synthesis time, allowing to trade throughput for hardware resources and power consumption. To demonstrate the efficiency of our proposal, we implement high-complexity convolutional neural networks on the Xilinx Virtex-7 VC709 FPGA board. While reaching a better accuracy than comparable designs, we can target either high throughput or low power. We measure a throughput up to 27 000 fps at ≈7W or up to 8.36 TMAC/s at ≈13 W.

关键词： Neurons Parallel processing Random access memory field programmable gate arrays Hardware throughput Neural networks

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High performance binary neural networks on the Xeon+FPGA™ platform

High performance binary neural networks on the Xeon+FPGA™ p...

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international conference on field programmable logic and applications

作者： Duncan J. M. Moss Eriko Nurvitadhi Jaewoong Sim Asit Mishra Debbie Marr Suchit Subhaschandra Philip H. W. Leong FPGA Product Team Intel Corporation The University of Sydney Accelerator Architecture Lab

Convolutional neural networks (CNNs) are deployed in a wide range of image recognition, scene segmentation and object detection applications. Achieving state of the art accuracy in CNNs often results in large models and complex topologies that require significant compute resources to complete in a timely manner. Binarised neural networks (BNNs) have been proposed as an optimised variant of CNNs, which constrain the weights and activations to +1 or -1 and thus offer compact models and lower computational complexity per operation. this paper presents a high performance BNN accelerator on the Intel®Xeon+FPGA™ platform. the proposed accelerator is designed to take advantage of the Xeon+FPGA system in a way that a specialised FPGA architecture can be targeted for the most compute intensive parts of the BNN whilst other parts of the topology can be handled by the Xeon™ CPU. the implementation is evaluated by comparing the raw compute performance and energy efficiency for key layers in standard CNN topologies against an Nvidia Titan X Pascal GPU and other published FPGA BNN accelerators. the results show that our single-package integrated Arria™ 10 FPGA accelerator coupled with a high-end Xeon CPU can offer comparable performance and better energy efficiency than a high-end discrete Titan X GPU card. In addition, our solution delivers the best performance compared to previous BNN FPGA implementations.

关键词： field programmable gate arrays Graphics processing units Topology Computer architecture Performance evaluation Network topology IP networks

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An XDL Alternative for Interfacing RapidSmith and Vivado 26

An XDL Alternative for Interfacing RapidSmith and Vivado

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26th international conference on field-programmable logic and applications (FPL)

作者： Townsend, thomas Nelson, Brent Wirthlin, Mike Brigham Young Univ Dept Elect & Comp Engn NSF Ctr High Performance Reconfigurable Comp CHRE Provo UT 84602 USA

ISBN: (纸本)9782839918442

In recent years, the RapidSmith CAD tool [1] has been used with ISE to create custom CAD tools targeting Xilinx FPGAs. this tool flow was based on the Xilinx Design Language (XDL), a human-readable representation of a netlist that contains placement and routing information. the XDL interface also provided device representation files (XDLRC files), detailing the available resources of a given FPGA part. Using RapidSmith, a Xilinx design could be exported out of ISE at any stage of the design flow, manipulated in RapidSmith (logic modification, place, or route), and imported back into ISE to complete the remainder of implementation. © 2016 EPFL.

关键词： field programmable gate arrays (FPGA)

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