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HeteroSim: A Heterogeneous CPU-FPGA Simulator 26

HeteroSim: A Heterogeneous CPU-FPGA Simulator

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26th international conference on field-programmable logic and applications (FPL)

作者： Feng, Liang Liang, Hao Sinha, Sharad Zhang, Wei Hong Kong Univ Sci & Technol Dept Elect & Comp Engn Kowloon Hong Kong Peoples R China

ISBN: (纸本)9782839918442

Heterogeneous computing is rapidly gaining increased attention due to the promise it holds in overcoming power and performance walls in traditional computing systems. With its focus on customized processing nodes dedicated to the different tasks in an application, it is hoped that these walls will be overcome. therefore, CPU-FPGA co-architectures are also gaining ground in application areas like recognition, mining, search, datacenter etc. However, research in CPU-FPGA co-architecture is constrained by the available synthesis and simulation tools which do not provide an integrated system level simulation and architectural exploration environment. this becomes critical when we incorporate novel memory hierarchies, multi-processor chip architectures, hardware level cache coherence etc. In this paper, we describe our open source and integrated system level simulator and architecture exploration tool called HeteroSim. It supports x86 based multi-core processor combined with a FPGA via bus-based architecture. It allows integrated system level simulation and returns performance metrics to understand application performance with respect to the simulated architectural configuration.

关键词： field programmable gate arrays (FPGA)

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Transparent FPGA Flow 26

Transparent FPGA Flow

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26th international conference on field-programmable logic and applications (FPL)

作者： Delporte, Baptiste Convers, Anthony Rigamonti, Roberto Dassatti, Alberto HEIG VD Sch Business & Engn Vaud HES SO REDS Inst CH-1400 Yverdon Switzerland

ISBN: (纸本)9782839918442

Heterogeneous computing has recently emerged as a way to circumvent the physical and technological limitations in the design of computing devices. the pressure exerted by the ever-growing demand of increased performances has eventually made the long-awaited dream of having a traditional CPU paired up with an FPGA a reality [1], [2]. FPGAs have proven indeed to be a viable solution for energy efficient high-performance computing [3], [4], [5]. However, while providing the system integrator a very compact and cost effective way to add advanced functionalities to products, this technological evolution has dramatically raised the overall complexity of the system: Exploiting the available capabilities now requires a wide range of competencies which are not always in the background of a company or institution. this requires a considerable effort at development time and often limits the applicability to a reduced set of supported brands/models, while being effective only when predicted usage patterns match the actual ones. High-Level Synthesis (HLS) [6] partially mitigates the above-mentioned problems by removing the language-barrier, but compiling and deploying a bitstream is an extremely long process, and again its development requires establishing a-priori usage patterns that might lead to a suboptimal usage of the available hardware. © 2016 EPFL.

关键词： field programmable gate arrays (FPGA)

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JetStream: An Open-Source High-Performance PCI Express 3 Streaming Library for FPGA-to-Host and FPGA-to-FPGA Communication 26

JetStream: An Open-Source High-Performance PCI Express 3 Str...

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26th international conference on field-programmable logic and applications (FPL)

作者： Vesper, Malte Koch, Dirk Vipin, Kizheppatt Fahmy, Suhaib A. Univ Manchester Sch Comp Sci Manchester M13 9PL Lancs England Mahindra Ecole Cent Hyderabad Andhra Pradesh India Univ Warwick Sch Engn Coventry CV4 7AL W Midlands England

ISBN: (纸本)9782839918442

Many FPGA-based accelerators are constrained by the available resources and multi-FPGA solutions can be necessary for building more capable systems. Available PCIe solutions provide only FPGA-to-Host communication. In this paper we present JetStream, an open-source1 modular PCIe 3 library, supporting not only fast FPGA-to-Host communication, but also allowing direct FPGA-to-FPGA communication which fully bypasses the memory subsystem. the direct mode saves memory bandwidth for multicast modes and permits to connect multiple FPGAs in various software defined topologies. We show the benefits of JetStream with a large FIR filter spanning four FPGA boards, achieving throughputs of up to 7.09 GB/s per link. Utilizing direct FPGA-to-FPGA transfers reduces the required memory bandwidth by up to 75%.

关键词： field programmable gate arrays (FPGA)

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Harnessing programmable SoCs to Develop Cost-effective Network Quality Monitoring Devices 26

Harnessing Programmable SoCs to Develop Cost-effective Netwo...

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26th international conference on field-programmable logic and applications (FPL)

作者： Ruiz, M. Ramos, J. Sutter, G. Lopez-Buedo, S. Lopez de Vergara, J. E. Sisterna, C. Univ Autonoma Madrid High Performance Comp & Networking Res Grp E-28049 Madrid Spain NAUDIT HPCN Madrid Spain Univ Nacl San Juan Inst Invest Antisism San Juan Argentina

ISBN: (纸本)9782839918442

Networks are currently essential for computing: It is therefore essential to guarantee the quality of network links in order to ensure a proper operation of computing systems. However, a widespread deployment of network monitoring devices might not be economically feasible. In this paper, we propose the use of programmable System-on-Chip FPGAs (PSoCs) for enabling a comprehensive testing of networks. Software-only solutions are no longer valid, because the timescales of current networks call for custom-hardware solutions. thus, we show that PSoCs are a perfect fit for network quality monitoring devices, by mapping the required measurements to the capabilities of such devices. In order to demonstrate the benefits of PSoCs to monitor the quality of network links, we have developed a prototype based on Xilinx Zynq that is capable of measuring the key performance indicators of Gigabit Ethernet networks, namely: available bandwidth, packet loss, delay and jitter. the monitoring probe features GPS-based timestamping, thus enabling the construction of network delay maps. We present the benefits of the proposed approach in terms of cost and simplicity, and we also show how it could be expanded to multi-Gb/s networks.

关键词： Cost effectiveness

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Runtime-Quality Tradeoff in Partitioning Based Multithreaded Packing 26

Runtime-Quality Tradeoff in Partitioning Based Multithreaded...

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26th international conference on field-programmable logic and applications (FPL)

作者： Vercruyce, Dries Vansteenkiste, Elias Stroobandt, Dirk Univ Ghent ELIS Dept Comp Syst Lab Ghent Belgium

ISBN: (纸本)9782839918442

It takes a long time to generate a configuration for an FPGA starting from a description of a digital circuit in a hardware design language. this configuration should have a high quality so that the FPGA resources are used in an efficient way with the maximum clock frequency and minimizing the power consumption. In this work we present two new packing algorithms that obtain better quality and faster runtimes when compared to the frequently used AAPack packer. the partitioning based methodology allows us to exploit the advantage of multi-threading on commodity hardware. Firstly we demonstrate the benefits of our fully partitioning based PartSA packer. Existing packers with a partitioning based approach have problems with the cluster size and bandwidth constraint of the functional blocks. We added a fast simulated annealing step after partitioning to solve these problems. A gain of 26% in total wirelength is obtained while reaching up to 2.3x faster packing runtimes for large circuits on a CPU with four cores. Unfortunately the PartSA packer can not be used for architectures without a complete crossbar in the functional blocks. therefore a second packer is proposed that combines the benefits of partitioning based and seed based packing. MultiPart has up to 4x faster packing runtimes while still having a gain of 20% in total wirelength.

关键词： field programmable gate arrays (FPGA)

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TeSHoP : A Temperature Sensing based Hotspot-Driven Placement Technique for FPGAs 26

TeSHoP : A Temperature Sensing based Hotspot-Driven Placemen...

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26th international conference on field-programmable logic and applications (FPL)

作者： Lu, Weina Hu, Yu Ye, Jing Li, Xiaowei Chinese Acad Sci Inst Comp Technol State Key Lab Comp Architecture Beijing 100864 Peoples R China Chinese Acad Sci Grad Univ Beijing 100864 Peoples R China

ISBN: (纸本)9782839918442

the rapid shrinking of the feature size in CMOS technology has significantly increased the power density of integrated circuits, leading to excessive temperature. though online thermal management techniques such as DVFS and task migration can mitigate the temperature issue, but usually incur significant performance penalty. therefore, it is crucial to optimize temperature at the design stage. In this work, we propose the TeSHoP, a Temperature Sensing based Hotspot-Driven Placement technique for FPGAs. Firstly, the un-optimized circuit along with a sensor network is run in FPGA to obtain the real temperature profile of the circuit. then, based on the temperature profile, we proceed a one-off adjustment of the circuit placement for hotspot optimization. the optimization is modeled as a Hyper Minimum Bipartite Matching problem for solving. We implement the whole optimization flow in a real FPGA, with extension of the VTR-to-Bitstream tool. Experimental results on Xilinx Virtex-6 FPGA show that the reduction of peak temperature and the improvement of thermal uniformity can be up to 7.5 degrees C and 13.9% respectively.

关键词： field programmable gate arrays (FPGA)

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DT-CGRA: Dual-Track Coarse-Grained Reconfigurable Architecture for Stream applications 26

DT-CGRA: Dual-Track Coarse-Grained Reconfigurable Architectu...

引用

26th international conference on field-programmable logic and applications (FPL)

作者： Fan, Xitian Li, Huimin Cao, Wei Wang, Lingli Fudan Univ State Key Lab ASIC & Syst 825 Zhangheng Rd Shanghai 201203 Peoples R China

ISBN: (纸本)9782839918442

this paper presents a new type of coarse-grained reconfigurable architecture (CGRA) for the object inference domain in machine learning. the proposed CGRA is optimized for stream processing and a correspondent programming model called dual-track model is proposed. the CGRA is realized in Verilog HDL and implemented in SMIC 55 nm process, with the footprint of 3.79 mm(2) and consuming 1.79 W at 500 MHz. To evaluate the performance, eight machine-learning algorithms including HOG, CNN, k-means, PCA, SPM, linear-SVM, Softmax and Joint-Bayesian are selected as benchmarks. these algorithms cover a general machine learning flow in object inference domain: feature extraction, feature selection and inference. the experimental results show that the proposed CGRA can gain 1443x average energy efficiency comparing to the Intel i7-3770 CPU and 7.82x energy efficiency comparing to a high performance FPGA solution [19].

关键词： coarse-grained reconfigurable architecture domain-specific computing machine learning object inference

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Annotation-Based Finite-State Transducers on Reconfigurable Devices 26

Annotation-Based Finite-State Transducers on Reconfigurable ...

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26th international conference on field-programmable logic and applications (FPL)

作者： Polig, Raphael Atasu, Kubilay Hagleitner, Christoph Xu, theresa Nakayama, Akihiro IBM Res Zurich Ruschlikon Switzerland IBM Syst Toronto ON Canada IBM Watson Tokyo Japan

ISBN: (纸本)9782839918442

With the ever growing amount of unstructured data, high-speed content analysis becomes ever more important. Enabling efficient search functions to help locate specific and relevant information hidden in this big data is a crucial task of today's enterprise systems, and can lead to valuable insights. A key component of content analysis systems are text parsers, which transform unstructured text data into structured information. Cascaded grammars offer a popular and powerful representation of text parsers by enabling the definition of more complex patterns in terms of simpler ones in a hierarchical fashion. this work presents a compilation framework to generate an optimized FPGA pipeline from a cascaded grammar description. We also describe the system integration and the way FPGA-based accelerators can be used as part of larger analysis tasks within Unstructured Information Management Application (UIMA) pipelines. We compare the performance of the hardware-accelerated system and a commercial software implementation using real-life UIMA pipelines from the healthcare domain. We show that the FPGA-accelerated system processes the parsing stage of a UIMA pipeline up to 31 times faster than the software implementation running on a high-end server, which results in an acceleration of up to 5 times for the complete pipeline.

关键词： field programmable gate arrays (FPGA)

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Efficient and Reliable High-Level Synthesis Design Space Explorer for FPGAs 26

Efficient and Reliable High-Level Synthesis Design Space Exp...

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26th international conference on field-programmable logic and applications (FPL)

作者： Liu, Dong Schafer, Benjamin Carrion Hong Kong Polytech Univ Dept Elect & Informat Engn Hong Kong Hong Kong Peoples R China

ISBN: (纸本)9782839918442

this paper presents a dedicated High-Level Synthesis (HLS) Design Space Explorer (DSE) for FPGAs. C-based VLSI design has the advantage over conventional RTL design that it allows the generation of micro-architectures with unique area vs. performance trade-offs without having to modify the original behavioral description (in this work area vs. latency). this is typically done by modifying the Functional Unit (FU) constraint file or setting different synthesis directives e.g. unroll loops or synthesize arrays as RAM or registers. the result of the design space exploration is a set of Pareto-optimal designs. In this work, we first investigate the quality of the exploration results when using the results reported after HLS (in particular the area) to guide the explorer in finding Pareto-optimal designs. We found that due to the nature of how HLS tools pre-characterize, the area and delay of basic logic primitives and the FPGAs internal structure the area results are not accurate and hence making it necessary to perform a logic synthesis after each newly generated design. this in turn leads to unacceptable long running time. this work therefore presents a dedicated DSE for FPGAs based on a pruning with adaptive windowing method to extract the design candidates to be further (logic) synthesized after HLS. the adaptive windowing is based on a learning method inspired from Rival Penalized Competitive Learning (RPCL) model in order to classify which designs need to be synthesized to find the true Pareto-optimal designs. Results show that our method leads to similar results compared to an explorer which performs a logic synthesis for each newly generated design, while being much faster.

关键词： field programmable gate arrays (FPGA)

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Automated Extra Pipeline Analysis of applications mapped to Xilinx UltraScale plus FPGAs 26

Automated Extra Pipeline Analysis of Applications mapped to ...

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26th international conference on field-programmable logic and applications (FPL)

作者： Ganusov, Ilya Fraisse, Henri Ng, Aaron Possignolo, Rafael Trapani Das, Sabya Xilinx Inc 2100 Log Dr San Jose CA 95124 USA Univ Calif Santa Cruz Dept Comp Engn Santa Cruz CA 95064 USA

ISBN: (纸本)9782839918442

this paper describes the methodology and algorithms behind extra pipeline analysis tools released in the Xilinx Vivado Design Suite version 2015.3. Extra pipelining is one of the most effective ways to improve performance of FPGA applications. Manual pipelining, however, often requires significant efforts from FPGA designers who need to explore various changes in the RTL and re-run the flow iteratively. the automatic pipelining approach described in this paper, in contrast, allows FPGA users to explore latency vs. performance trade-offs of their designs before investing time and effort into modifying RTL. We describe algorithms behind these tools which use simple cut heuristics to maximize performance improvement while minimizing additional latency and register overhead. To demonstrate the effectiveness of the proposed approach, we analyse a set of 93 commercial FPGA applications and IP blocks mapped to Xilinx UltraScale+ and UltraScale generations of FPGAs. the results show that extra pipelining can provide from 18% to 29% potential Fmax improvement on average. It also shows that the distribution of improvements is bimodal, with almost half of benchmark suite designs showing no improvement due to the presence of large loops. Finally, we demonstrate that highly-pipelined designs map well to UltraScale+ and UltraScale FPGA architectures. Our approach demonstrates 19% and 20% Fmax improvement potential for the UltraScale+ and UltraScale architectures respectively, with the majority of applications reaching their loop limit through pipelining.

关键词： field programmable gate arrays (FPGA)

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