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Accelerating particle identification for high-speed data-filtering using OpenCL on FPGAs and other architectures OpenCL for FPGA in High Energy Physics 26

Accelerating particle identification for high-speed data-fil...

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26th international conference on field-programmable logic and applications (FPL)

作者： Sridharan, Srikanth Durante, Paolo Faerber, Christian Neufeld, Niko CERN LHCb Geneva Switzerland

ISBN: (纸本)9782839918442

the upgrade of the LHCb experiment at CERN envisions a Data Acquisition and Event Filtering system that captures 100% of the data generated by the various subdetectors, which measure with great precision the 40 million collisions per second of protons in CERN's Large Hadron Collider. the sensor readings result in about 40 Tbit/s of data, which need to be processed on a large computer farm. Since the computation on CPUs, as it is currently done, does not scale well, it is necessary to accelerate a good portion of the code to meet the computational demands of the proposed system. We are therefore looking for means to accelerate the most time-consuming parts of the event-filtering code. the Ring Imaging Cherenkov (RICH) detectors are one of the component detectors of the overall LHCb experiment. the Cherenkov photon that hits the detector are processed to determine the track of the original particle that caused these photons. the particle velocity and mass, derived from the Cherenkov angle, is used to identify the particle. the entire RICH photon reconstruction algorithm accounts for 50% of the second High Level Trigger (HLT) process and Cherenkov angle reconstruction comprises about 20% of the RICH and is a good candidate for acceleration. An OpenCL implementation of Cherenkov angle reconstruction algorithm that calculates the trajectory of Photons in the RICH detector was developed. the paper looks at the results of the OpenCL implementation of the algorithm on the Nallatech 385 card with Altera Strati x V FPGA, Nvidia GeForce GTX 690 GPU card and the Intel Xeon processor for comparison. While the two GPUs are 3.6X faster than a single FPGA, the FPGA is 3.4X better than two GPUs and 6.6X better than two multicore CPUs when energy efficiency is factored. Although significant speedup of computation was achieved on all the above architectures by using OpenCL, a good portion of the gain was lost due to the overhead of data transfer and parallelism. Different strategies a

关键词： FPGA field prgrammable gate arrays OpenCL GPU GPGPU High throughput computing HTC LHCb HEP High Energy Physics CEKN

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A low bit-width parameter representation method for hardware-oriented convolution neural networks

A low bit-width parameter representation method for hardware...

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international conference on ASIC

作者： Qiang Chen Chen Xin Chenglong Zou Xinan Wang Bo Wang School of ECE The Key Laboratory of Integrated Microsystem Shenzhen China

Convolution neural networks (CNNs) have become the state-of-the-art technique for Artificial Intelligence (AI) applications. But they consume resources heavily both in computation and energy. Compressing the parameters to fewer bits is an effective way to reduce data quantity, making it possible to deploy CNNs on mobile, IoT and other resource-limited devices. the existing means need to re-train the entire networks and tune the parameters. this paper presents a convenient method to compress the parameters of trained CNN models without re-training and fine-tuning. Our method reduces the number of bits from 32 to 5-9 under the same networks and on the same dataset, with the loss of accuracy less than 1%. the logic power of a trained LeNet reduces by 70.58% on FPGA evaluation.

关键词： Quantization (signal) field programmable gate arrays Hardware Adders C++ languages Convolution Neural networks

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Debugging Framework for FPGA-based Soft Processors 15

Debugging Framework for FPGA-based Soft Processors

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15th international conference on field-programmable Technology (FPT)

作者： Sidler, David Eguro, Ken Swiss Fed Inst Technol Dept Comp Sci Zurich Switzerland Microsoft Res Redmond WA USA

ISBN: (纸本)9781509056026

Soft processors are one way to raise the computational abstraction of FPGAs while keeping the advantages of reconfigurable hardware, such as adaptability, deterministic performance and high performance/watt. Software developers can quickly build, test and deploy applications using familiar tools while still leveraging important optimizations such as application-specific custom instructions. However, they also present unique debugging problems. For example, the higher-level programming abstraction runs contradictory to classical low-level debugging tools like logic analyzers. In this work we present a debugging framework for FPGA-based soft processors that enables step-by-step debugging at the level of all soft processor instructions, timetravel debugging, post-mortem memory dumps, and performance metrics. By using knowledge about the soft processor's internals, our framework can capture execution traces up to 60x more space-efficient than traditional embedded logic analyzers.

关键词： Program processors Debugging Hardware Instruments field programmable gate arrays Tools Radiation detectors

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Time-borrowing platform in the Xilinx UltraScale+ family of FPGAs and MPSoCs 26

Time-borrowing platform in the Xilinx UltraScale+ family of ...

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26th international conference on field-programmable logic and applications, FPL 2016

作者： Ganusov, Ilya Devlin, Benjamin Xilinx Inc. 2100 Logic Drive San JoseCA95124-3400 United States

ISBN: (纸本)9782839918442

this paper presents enhancements to the Xilinx UltraScale+ clocking architecture to support fine-grain time-borrowing. Time borrowing improves performance by redistributing timing slack between fast and slow paths. the Ultra-Scale+ architecture introduces programmable hardware delays and pulse generators embedded in the clocking tree to support time-borrowing based both on clock skew scheduling and pulsed latches. this programmable hardware allows borrowing from a few picoseconds to multiple nanoseconds between sequential pipeline stages without any changes to RTL, placement or routing. Vivado algorithms automatically determine when to skew flip-flop clock or convert them to pulsed latches to achieve the highest possible performance. Using the default Vivado flow, this programmable time-borrowing platform delivers 5.5% Fmax increase on average over a suite of 89 industrial designs. It is especially effective on high-speed applications, delivering up to 13.7% Fmax increase on individual designs. We also demonstrate that using non-default features, such as delays cascades or increasing hold margin, can increase average performance gains to 7.4% and 8.5%, respectively. this platform incurs minimum area (less than 0.1% of total chip area) while staying robust in the presence of tight hold constraints and increasing process variation. © 2016 EPFL.

关键词： field programmable gate arrays (FPGA)

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Forming Student Groups with Student Preferences Using Constraint logic Programming 17th

Forming Student Groups with Student Preferences Using Constr...

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17th international conference on Artificial Intelligence - Methodology, Systems and applications (AIMSA)

作者： Tacadao, Grace Toledo, Ramon Prudencio Ateneo de Davao Univ Dept Comp Sci Roxas Ave Davao 8016 Philippines

ISBN: (纸本)9783319447483;9783319447476

Forming student groups must be carefully planned for a successful collaborative work. Since there is no consensus in the literature and in practice as to the strategy and parameters to use, a strategy that takes the teachers' and the students' perspectives was developed in this preliminary study. Furthermore, a program based on this strategy was also written using Constraint logic Programming (CLP). the parameters and conditions to use were obtained through a faculty survey and student interviews. Based on the results, the faculty does not regard teammate preferences as important while students prefer that these are given the utmost consideration. thus, cohorts produced are not only evaluated based on satisfied constraints but also on satisfied teammate preferences. Hence, the study demonstrates not only that CLP can be applied in the field of computer-supported group formation but also that a grouping strategy can both include parameter constraints and teammate preferences.

关键词： Students

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Cost-Oriented Open Source Automation Potential Application in Industrial Control applications

Cost-Oriented Open Source Automation Potential Application i...

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17th IFAC conference on international Stability, Technology and Culture (TECIS)

作者： Hoxha, Valmir Bula, Ines Shala, Muzafer Hajrizi, Edmond UBT Fac Mechatron Management Pristina Kosovo

One of the most cost effective ways to make system control (automation) is by using open source hardware and software, in order to be cost oriented besides the price the systems need to be implemented in reasonable time frame and also needs to be reliable and safe. In this paper we will treat and justify the cases of using the Open Source Hardware and Software, in comparison to industry standard programmable logic Controllers (PLC). Also we will discuss about the point of system complexity where the cost reduction will not justify the time spend to build the interfacing of sensors, digital and analog I/O for the open source Hardware. (C) 2016, IFAC (international Federation of Automatic Control) Hosting by Elsevier Ltd. All rights reserved.

关键词： Open Source Cost Oriented Automation PLC Micro-controllers Sensors Industry Developing countries

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FPGA based Hardware Accelerator for KAZE Feature Extraction Algorithm 15

FPGA based Hardware Accelerator for KAZE Feature Extraction ...

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15th international conference on field-programmable Technology (FPT)

作者： Kalms, Lester Elhossini, Ahmed Juurlink, Ben Tech Univ Berlin Embedded Syst Architectures AE Einsteinufer 17 D-10587 Berlin Germany Al Azhar Univ Dept Comp & Syst Fac Engn Cairo Egypt

ISBN: (纸本)9781509056026

Processing and understanding of visual data has a significant importance in many applications such as robotics and vision aid devices. Extracting image features is one of the important tasks in computer vision. this paper focuses on KAZE features algorithm, due to its good performance. KAZE features is a multi-scale 2D feature detection and description algorithm. It describes 2D features in a non-linear scale space by means of non-linear diffusion filtering. In this paper, the algorithm was optimized for speed, memory usage and portability. the paper presents a hardware accelerator for the scale-space analysis part of the algorithm on FPGA. A high speed-up has been achieved by this accelerator by parallelizing several parts of the algorithm and reducing the memory bandwidth.

关键词： Feature extraction Algorithm design and analysis Hardware Aerospace electronics field programmable gate arrays Ports (Computers) Random access memory

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Model Checking Reconfigurable Petri Nets with Maude 9th

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9th international conference on Graph Transformation in Memory of Hartmut Ehrig (ICGT) held as part of conference on Software Technologies - applications and Foundations (STAF)

作者： Padberg, Julia Schulz, Alexander Hamburg Univ Appl Sci Hamburg Germany

ISBN: (纸本)9783319405308;9783319405292

Model checking is a widely used technique to prove properties such as liveness, deadlock or safety for a given model. Here we introduce model checking of reconfigurable Petri nets. these are Petri nets with a set of rules for changing the net dynamically. We obtain model checking by converting reconfigurable Petri nets to specific Maude modules and using then the LTLR model checker of Maude. the main result of this paper is the correctness of this conversion. We show that the corresponding labelled transitions systems are bisimular. In an ongoing example reconfigurable Petri nets are used to model and to verify partial dynamic reconfiguration of field programmable gate arrays.

关键词： Reconfigurable Petri nets Rewrite logic Maude Model checking field programmable gate array Dynamic partial reconfiguration

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17th international conference on Advanced Batteries, Accumulators and Fuel Cells, ABAF 2016

17th International Conference on Advanced Batteries, Accumul...

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17th international conference on Advanced Batteries, Accumulators and Fuel Cells, ABAF 2016

ISBN: (纸本)9781607685395

the proceedings contain 41 papers. the topics discussed include: FEM model of the lithium ion battery nail test;design, build and validation of a low-cost programmable battery cycler;the second life ageing of the NMC/C electric vehicle retired Li-ion batteries in the stationary applications;Li-ion battery charging efficiency;pulse power capability estimation of lithium titanate oxide-based batteries;finite element model of discharging and temperature field of the lithium ion battery;high efficiency fast-chargers for lead-acid batteries;Li-ion battery deep discharge degradation;impulse diagnostic test of battery and load influence;compact high-efficiency Li-ion fast-charger;significance of the capacity recovery effect in pouch lithium-sulfur battery cells;combined effect of acryl fibers and TiO2 in negative active mass of lead-acid accumulator;automatic li-ion accumulator measuring stand;finite element approach of current density distribution in lead acid battery grid;delayed thermal runaway investigation on commercial 2.6 Ah NCM-LCO based 18650 lithium ion cells with accelerating rate calorimetry;curing of positive electrode mass for lead acid battery studied by XRD;XRD study of lead sulfate crystal growth in sulfuric acid solution;and pulse deposition of zinc in electrolytes with reduced zinc oxide solubility.

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Exploring Static and Dynamic Flash-based FPGA Design Topologies 34

Exploring Static and Dynamic Flash-based FPGA Design Topolog...

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34th IEEE international conference on Computer Design (ICCD)

作者： Abusultan, Monther Khatri, Sunil P. Texas A&M Univ ECE Dept College Stn TX 77843 USA

ISBN: (纸本)9781509051427

field programmable gate arrays (FPGAs) are the implementation platform of choice when it comes to design flexibility. However, SRAM-based FPGAs suffer from high power consumption, prolonged boot delays (due to the volatility of the configuration bits), and a significant area overhead (due to the use of 5T SRAM cells for the configuration bits). Floating gate (flash) based FPGAs can avert these problems. this paper presents a study of flash-based FPGA designs (both static and dynamic), and presents the tradeoff of delay, power dissipation and energy consumption of the various designs. Our work differs from previously proposed flash-based FPGAs, since we embed the flash transistors (which store the configuration bits) directly within the logic and interconnect fabrics. We also present a detailed description of how the programming of the configuration bits is accomplished. Our delay and power estimates are derived from circuit level simulations. Our proposed static flash-based LUT structure yields 10% faster operation, 12% lower dynamic power dissipation, 21% lower energy consumption and 29% lower static power dissipation compared to a traditional SRAM-based LUT. We also show that, for high performance applications, a dynamic flash-based LUT can achieve further performance improvements (32% lower delay) with higher energy consumption (37% higher) compared to an SRAM-based LUT. We also show that a flash-based interconnect structure provides 89% lower delay and 71% lower overall power consumption compared to the traditional interconnect structure used in SRAM-based FPGAs.

关键词： field programmable Gate Arrays Flash-based FPGA

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