SRAM-based fieldprogrammable Gate Arrays (FPGAs) have been used in the aerospace application for more than a decade. Unfortunately, a significant disadvantage of these devices is their sensitivity to radiation effect...
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ISBN:
(纸本)9781467395199
SRAM-based fieldprogrammable Gate Arrays (FPGAs) have been used in the aerospace application for more than a decade. Unfortunately, a significant disadvantage of these devices is their sensitivity to radiation effects that can cause bit flips in memory elements and ionisation induced faults in semiconductors, commonly known as Single Event Upsets (SEUs). An early dependability analysis on SRAM FPGA-based safety-critical application will enable the designers to develop a more reliable and robust design complying with design requirements, such as the DO-254 standard. We propose a methodology based on probabilistic model checking, to analyze the dependability and performability properties of such designs to guide design decisions. Probabilistic model checking is a well known formal verification technique, and the main advantage is that the analysis is exhaustive, which results in numerically exact answers to the temporal logic queries that contrast with discrete-event simulations. In the proposed methodology, starting from the high-level description of a system, a Markov (reward) model is constructed from the extracted Control Data Flow Graph (CDFG). Various dependability and performability related properties are then verified automatically using the PRISM model checker tool.
In this work, a secure short messaging service (SMS)-based communication interface is designed. the interface has applications in the internet of things (IoT) such as machine to machine (M2M) communications, and human...
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ISBN:
(纸本)9781509009169
In this work, a secure short messaging service (SMS)-based communication interface is designed. the interface has applications in the internet of things (IoT) such as machine to machine (M2M) communications, and human-operated remote system management. the case study of waking a personal computer remotely is considered, and a complete proof-of-concept is implemented for this purpose, using a field-programmable gate array (FPGA)-based receiving device and an Android-based transmitting device. On the Android device, SMS messages are generated in software using a "rolling code" system based on linear feedback shift registers (LFSRs), then encrypted withthe extended tiny encryption algorithm (XTEA) cipher. the FPGA employs both hardware XTEA decryption, and hardware systems to validate incoming messages.
this paper presents a framework for hardware and software co-design to building systems designed to driver assistant using computer vision. this work is part of a doctoral research project nearing completion. To valid...
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this paper presents a framework for hardware and software co-design to building systems designed to driver assistant using computer vision. this work is part of a doctoral research project nearing completion. To validate the model, a modular pedestrian detection is implemented by comparing the results obtained with other design.
this paper presents a novel reconfigurable circuit capable of implementing the entire family of 4-phase latch protocols. the architecture utilizes look-up-table based reconfigurable logic structures and fixed signal p...
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this paper presents a novel reconfigurable circuit capable of implementing the entire family of 4-phase latch protocols. the architecture utilizes look-up-table based reconfigurable logic structures and fixed signal paths. the implemented circuit creates a fabric to realize a variety of high speed and low power controllers for asynchronous circuits on FPGAs. the circuit is implemented on the IBM Artisan 65nm node and its performance is compared with implementations on a Xilinx Virtex-5 chip that is manufactured on a similar node. A 4× improvement in speed and 3.3× improvement in energy per cycle is achieved.
this PhD work presents a potential architecture and implementation for an FPGA-based all digital antenna array transmitter for wireless radio communications. By enabling the design of antenna arrays without external D...
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this PhD work presents a potential architecture and implementation for an FPGA-based all digital antenna array transmitter for wireless radio communications. By enabling the design of antenna arrays without external Digital-to-Analog Converters (DACs), external upconversion stages and without complex layouts, the analog front-end can be summed up to just amplification, filtering and radiation.
In this paper, a configurable many-core hardware/software architecture is proposed to efficiently execute the widely known and commonly used K-means clustering algorithm. A prototype was designed and implemented on a ...
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In this paper, a configurable many-core hardware/software architecture is proposed to efficiently execute the widely known and commonly used K-means clustering algorithm. A prototype was designed and implemented on a Xilinx Zynq-7000 All programmable SoC. A single core configured withthe slowest configuration achieves a 10× speed-up compared to the software only solution. the system is fully scalable and capable of achieving much higher speed-ups by increasing its parallelism.
Deploying advanced Simultaneous Localisation and Mapping, or SLAM, algorithms in autonomous low-power robotics will enable emerging new applications which require an accurate and information rich reconstruction of the...
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Deploying advanced Simultaneous Localisation and Mapping, or SLAM, algorithms in autonomous low-power robotics will enable emerging new applications which require an accurate and information rich reconstruction of the environment. this has not been achieved so far because accuracy and dense 3D reconstruction come with a high computational complexity. this paper discusses custom hardware design on a novel platform for embedded SLAM, an FPGA-SoC, combining an embedded CPU and programmablelogic on the same chip. the use of programmablelogic, tightly integrated with an efficient multicore embedded CPU stands to provide an effective solution to this problem. In this work an average framerate of more than 4 frames/second for a resolution of 320×240 has been achieved with an estimated power of less than 1 Watt for the custom hardware. In comparison to the software-only version, running on a dual-core ARM processor, an acceleration of 2× has been achieved for LSD-SLAM, without any compromise in the quality of the result.
In recent years, the RapidSmith CAD tool [1] has been used with ISE to create custom CAD tools targeting Xilinx FPGAs. this tool flow was based on the Xilinx Design Language (XDL), a human-readable representation of a...
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In recent years, the RapidSmith CAD tool [1] has been used with ISE to create custom CAD tools targeting Xilinx FPGAs. this tool flow was based on the Xilinx Design Language (XDL), a human-readable representation of a netlist that contains placement and routing information. the XDL interface also provided device representation files (XDLRC files), detailing the available resources of a given FPGA part. Using RapidSmith, a Xilinx design could be exported out of ISE at any stage of the design flow, manipulated in RapidSmith (logic modification, place, or route), and imported back into ISE to complete the remainder of implementation.
the rapid growth of wire RC delay with technology scaling has put increasing pressure on FPGA architects to make more efficient use of the different layers available in the metal stack. While commercial FPGA architect...
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the rapid growth of wire RC delay with technology scaling has put increasing pressure on FPGA architects to make more efficient use of the different layers available in the metal stack. While commercial FPGA architectures have implemented the majority of inter-logic-block wiring on the lower metal layers and a small fraction of wires on the least-resistive upper metal layers, published explorations have largely ignored the question of how to exploit the different layers of the metal stack, focusing instead on very simple interconnect topologies and physical models. We generate VPR architectures and detailed area and delay models at the 22nm node and present enhancements to VPR that enable us to describe and evaluate complex interconnect topologies. We use our new architectures and tool enhancements to explore complex interconnect patterns suitable for modern unidirectional architectures and suggest topologies to connect wires on the semi-global and global metal layers. the proposed topologies improve the critical path routing delay by 17% compared to architectures with no global layer wires, and by 5-13% compared to architectures with global layer wires using the default VPR switch pattern.
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