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Overoptimistic Voltage Scaling in Pre-Error AVS Systems and Learning-Based Alleviation 29

Overoptimistic Voltage Scaling in Pre-Error AVS Systems and ...

引用

29th IEEE international System-on-Chip conference (SOCC)

作者： Ting, Yi-Hsuan Wang, Chih-Yang Chang, Yu-Sian Lin, Tay-Jyi Chang, Shih-Chieh Wang, Jinn-Shyan Natl Chung Cheng Univ CCU Dept Comp Sci & Informat Engn Minxiong Township Chiayi Taiwan Natl Tsing Hua Univ Dept Comp Sci Hsinchu Taiwan CCU SoC Ctr Minxiong Township Chiayi Taiwan CCU AIM HI Ctr Minxiong Township Chiayi Taiwan CCU Dept Elect Engn Minxiong Township Chiayi Taiwan

ISBN: (纸本)9781509013678

In-situ timing error detection and correction mechanisms (such as Razor) monitor the performance of actual datapaths, and are believed more resilient in adaptive voltage scaling (AVS) systems, especially when considering local variations. However, Razor has serious hold time problems, of which the overwhelming buffer padding makes it infeasible in advanced process technologies. Pre-error (or in-situ canary) detection was then proposed as an alternative. In addition, sophisticated error correction is no longer needed accordingly. the Markov chain model was proposed by independent researchers to design the pre-error AVS controller to explicitly trade quality for energy, where the input patterns are assumed to have a Gaussian delay distribution. For error-tolerant applications where few errors are acceptable, pre-error AVS is shown more efficient than Razor-based approaches. In this paper, a pre-error AVS system has been constructed on a 28nm FPGA platform with programmable power supply. It is observed that when the delay distributions are time-varying and non-Gaussian, overoptimistic voltage scaling (OVS) can occur and may lead to serious problems in pre-error AVS. To resolve the OVS problem, we propose to insert certain logics to collect the delay criticality information, which is fed into a Q-learning model to create the learning-based AVS. Experimental results show that the proposed scheme saves 10.50% power while reducing 0.16% error rate for random inputs and saves 12.51% power while reducing 0.06% error rate for non-random inputs, compared with the original pre-error AVS that assumes a static Gaussian delay distribution.

关键词： Delays field programmable gate arrays logic gates Markov processes Decoding Clocks

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An FPGA-based high-throughput stream join architecture

An FPGA-based high-throughput stream join architecture

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international conference on field programmable logic and applications

作者： Charalabos Kritikakis Grigorios Chrysos Apostolos Dollas Dionisios N. Pnevmatikatos Microprocessor and Hardware Laboratory Technical University of Crete Chania Greece Technical University of Crete Chania GR

Stream join is a fundamental operation that combines information from different high-speed and high-volume data streams. this paper presents an FPGA-based architecture that maps the most performance-efficient stream join algorithm, i.e. ScaleJoin, to reconfigurable logic. the system was fully implemented on a Convey HC-2ex hybrid computer and the experimental performance evaluation shows that the proposed system outperforms by up to one order of magnitude the corresponding fully optimized parallel software-based solution running on a high-end 48-core multiprocessor platform. the proposed architecture can be used as a generic template for mapping stream processing algorithms to reconfigurable logic, taking into consideration real-world challenges.

关键词： field programmable gate arrays

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A low-power MTJ-based nonvolatile FPGA using self-terminated logic-in-memory structure

A low-power MTJ-based nonvolatile FPGA using self-terminated...

引用

international conference on field programmable logic and applications

作者： Daisuke Suzuki Takahiro Hanyu Frontier Research Institute for Interdisciplinary Sciences Tohoku University Sendai Japan Research Institute of Electrical Communication Tohoku University Sendai Japan

A nonvolatile field-programmable gate array (NVFPGA), where both magnetic tunnel junction (MTJ) devices and greedy power-saving techniques are utilized, is proposed. Because the circuit components are shared among several MTJ devices by the use of logic-in-memory (LIM) structure, the number of leakage current paths is reduced, which results in leakage power reduction during power-on. Moreover, the use of the self-termination scheme, which automatically turns off the write current immediately after the desired data is written, makes it possible to minimize power consumption during the backup operation. In fact, the proposed NVFPGA exhibits a 90 % power reduction in comparison with that of a conventional SRAM-based FPGA under typical benchmark-circuit implementations.

关键词： field programmable gate arrays Phase change random access memory Benchmark testing MOS devices Multiplexing Transistors

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High-speed programmable FPGA Configuration through JTAG

High-speed programmable FPGA Configuration through JTAG

引用

international conference on field programmable logic and applications

作者： Ammon Gruwell Peter Zabriskie Michael Wirthlin Department of Electrical and Computer Engineering NSF Center for High-Performance Reconfigurable Computing (CHREC) Provo Utah

Over the past few decades, the use of reconfigurable computing for aerospace applications has become increasingly common despite its sensitivity to ionizing radiation. Tools are needed to test and implement fault-mitigation mechanisms to increase the reliability of FPGAs in space. this paper introduces a tool called the JTAG Configuration Manager (JCM) that provides high-speed programmable access to the configuration memory of Xilinx FPGAs using the JTAG serial protocol. the JCM consists of a linux-based software library running on an embedded ARM processor paired with a hardware state machine implemented in programmable logic. Two important uses of the JCM are configuration scrubbing and fault injection. the high-speed JTAG interface allows such operations to run at up to 60 MHz, which is several times faster than traditional JTAG FPGA configuration methods. the JCM also has access to the XADC on-chip temperature monitoring and the internal Boundary SCAN, making it useful for many testing and debugging applications.

关键词： field programmable gate arrays Hardware Circuit faults Software Testing Registers Software libraries

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LYNX: CAD for FPGA-based networks-on-chip

LYNX: CAD for FPGA-based networks-on-chip

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international conference on field programmable logic and applications

作者： Mohamed S. Abdelfattah Vaughn Betz Department of Electrical and Computer Engineering University of Toronto Toronto ON Canada

We present a computer-aided design (CAD) tool that automatically connects an FPGA application using an embedded network-on-chip (NoC). After discussing the CAD flow steps, we delve into the details of implementing transaction communication using our CAD tool. this request-reply type of communication requires special consideration on FPGAs, for example: low round-trip latency, fair arbitration and correct ordering. We show how to implement transaction communication using embedded NoCs, and show that we can improve latency, throughput and efficiency compared to soft buses generated by a commercial CAD tool.

关键词： field programmable gate arrays Ports (Computers) Design automation throughput Hardware design languages Clustering algorithms Multiplexing

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Efficient sum of absolute difference computation on FPGAs

Efficient sum of absolute difference computation on FPGAs

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international conference on field programmable logic and applications

作者： Martin Kumm Marco Kleinlein Peter Zipf Germany Digital Technology Group University of Kassel

An improved architecture for efficiently computing the sum of absolute differences (SAD) on FPGAs is proposed in this work. It is based on a configurable adder/subtractor implementation in which each adder input can be negated at runtime. the negation of both inputs at the same time is explicitly allowed and used to compute the sum of absolute values in a single adder stage. the architecture can be mapped to modern FPGAs from Xilinx and Altera. An analytic complexity model as well as synthesis experiments yield an average look-up table (LUT) reduction of 17.4% for an input word size of 8 bit compared to state-of-the-art. As the SAD computation is a resource demanding part in image processing applications, the proposed circuit can be used to replace the SAD core of many applications to enhance their efficiency.

关键词： Table lookup field programmable gate arrays Adders Complexity theory Motion estimation

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High-speed PCAP configuration scrubbing on Zynq-7000 All programmable SoCs

High-speed PCAP configuration scrubbing on Zynq-7000 All Pro...

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international conference on field programmable logic and applications

作者： Aaron Stoddard Ammon Gruwell Peter Zabriskie Michael Wirthlin Department of Electrical and Computer Engineering Brigham Young University Provo UT

Configuration scrubbing is a technique used for repairing Single Event Upsets (SEUs) within the configuration memory of an FPGA. Scrubbing approaches have been developed using hardware external to the FPGA communicating through a configuration port and using hardware within the FPGA by communicating with an internal configuration port (ICAP). More recent FPGAs such as the Xilinx Zynq 7-Series SoCs provide internal programmable processors that can configure the FPGA logic very rapidly using an internal Processor Configuration Access Port (PCAP). these SoC/FPGAs also provide automatic internal scrubbing through the use of high-speed readback and configuration error correction. this paper presents a novel form of FPGA configuration scrubbing for the Zynq-7000 SoC family by combining the high-speed PCAP configuration port with internal scrubbing. this novel scrubber corrects single-bit upsets in several microseconds and detects these upsets in 8 ms.

关键词： field programmable gate arrays Program processors Materials handling Random access memory Hardware Computer architecture Reliability

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Fast and area efficient adder for wide data in recent Xilinx FPGAs

Fast and area efficient adder for wide data in recent Xilinx...

引用

international conference on field programmable logic and applications

作者： Petter Källström Oscar Gustafsson Department of Electrical Engineering Linköping University Linköping Sweden

Most modern FPGAs have very optimised carry logic for efficient implementations of ripple carry adders (RCA). Some FPGAs also have a six input look up table (LUT) per cell, whereof two inputs are used during normal addition. In this paper we present an architecture that compresses the carry chain length to N/2 in recent Xilinx FPGA, by utilising the LUTs better. this carry compression was implemented by letting some cells calculate the carry chain in two bits per cell, while some others calculate the summary output bits. In total the proposed design uses no more hardware than the normal adder. the result shows that the proposed adder is faster than a normal adder for word length larger than 64 bits in Virtex-6 FPGAs.

关键词： Adders Microprocessors Delays field programmable gate arrays Table lookup Registers

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SoC and FPGA oriented high-quality stereo vision system

SoC and FPGA oriented high-quality stereo vision system

引用

international conference on field programmable logic and applications

作者： Yanzhe Li Kai Huang Luc Claesen Institute of VLSI Design Zhejiang University Hangzhou China Engineering Technology - Electronics-ICT Dept Hasselt University Diepenbeek Belgium

Stereo matching is a crucial step for acquiring depth information from stereo images. However, it is still challenging to achieve good performance in both speed and accuracy for various stereo vision applications. In this paper, a hardware-compatible stereo matching algorithm is proposed; its associated hardware implementation is also presented. the proposed algorithm can produce high-quality disparity maps with the use of mini-census transform, segmentation-based adaptive support weight and effective refinement. Moreover, the proposed implementation is optimized as a fully pipelined and scalable hardware system. the proposed design is evaluated based on the Middlebury benchmarks and the average overall error rate is 6.10%. the experimental results indicate that the accuracy is competitive with some state-of-art software implementations.

关键词： Image segmentation Hardware Algorithm design and analysis Software algorithms Transforms Software field programmable gate arrays

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Architectural exploration and implementation of an image processing chain with SpaceStudio™

Architectural exploration and implementation of an image pro...

引用

international conference on field programmable logic and applications

作者： Fellipe Montero Guy Bois Eric Jenn Kevin Duplantier Space Codesign Systems Inc. Montreal QC Canada IRT Saint-Exupéry Toulouse France

this demo presents a virtual platform and its system design methodology for MPSoC ARM-Based FPGA applied on a use case. the focus is on the architectural exploration step and architecture implementation step. the platform is enabled by the SpaceStudio ™ tool suite, which incorporates novel research in virtual platform modeling, performance profiling, architectural exploration and system generation for MPSoC. the methodology is applied on the Image-Based Position Monitoring function of TwIRTee, a small three-wheeled rover. TwIRTee is the demonstrator of the INGEQUIP project conducted at the Institut de Recherche Technologique of Toulouse (IRT Saint- Exupéry).

关键词： Computer architecture Image segmentation Monitoring field programmable gate arrays Algorithm design and analysis Compass

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