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A partial reconfiguration controller for Altera Stratix V FPGAs

A partial reconfiguration controller for Altera Stratix V FP...

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international conference on field programmable logic and applications

作者： Zhenzhong Xiao Dirk Koch Mikel Lujan The University of Manchester School of Computer Science UK

With the introduction of the Stratix V family, the FPGA vendor Altera is now fully supporting partial reconfiguration in all their recent FPGA devices. A distinct feature in the Altera architecture is that reconfigurable regions can be arbitrarily defined which is possible by writing a configuration mask prior to writing the actual configuration data to the FPGA fabric. In this paper, we will present details and the flow for implementing partial reconfiguration using Altera FPGAs, as well as a study on configuration bitstream sizes and configuration speeds for various resource and bounding-box aspect ratio variants. the results are used to build a partial reconfiguration controller that is featuring a lightweight but effective bitstream decompression module for greatly improving configuration speed on a DE5-net board.

关键词： field programmable gate arrays Fabrics Shift registers Writing Engines Acceleration Table lookup

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An investigation into a circuit based supply chain analyzer for FPGAs

An investigation into a circuit based supply chain analyzer ...

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international conference on field programmable logic and applications

作者： Jacob Couch John Arkoian Johns Hopkins University Applied Physics Laboratory Laurel MD

FPGAs are used in many long-life systems that serve mission-critical needs. the supply chain and life-cycle management of these devices have long relied on ensuring adequate controls are in place. In this paper, a technique is presented that provides measurement vectors by determining both characteristics of the supply properties of the FPGA and characteristics of aging of the FPGA. Asynchronous ring oscillators are placed throughout the FPGA, and the measurement of these oscillators is compared to other chips both within a manufacturing lot and between other manufacturing lots. through these non-invasive measurements, the “health history” of the FPGA can be evaluated and utilized in supply chain decisions before and during system operation.

关键词： field programmable gate arrays Supply chains Manufacturing Aircraft Aerospace electronics Current measurement Mission critical systems

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An FPGA-Based Low-Latency Network Processing for Spark Streaming 4

An FPGA-Based Low-Latency Network Processing for Spark Strea...

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4th IEEE international conference on Big Data (Big Data)

作者： Nakamura, Kohei Hayashi, Ami Matsutani, Hiroki Keio Univ Dept ICS Kohoku Ku 3-14-1 Hiyoshi Yokohama Kanagawa 2238522 Japan

ISBN: (纸本)9781467390057

Low-latency stream data processing is a key enabler for on-line data analysis applications, such as detecting anomaly conditions and change points from stream data continuously generated from sensors and networking services. Existing stream processing frameworks are classified into micro-batch and one-at-a-time processing methodology. Apache Spark Streaming employs the micro-batch methodology, where data analysis is repeatedly performed for a series of data arrived during a short time period, called a micro batch. A rich set of data analysis libraries provided by Spark, such as machine learning and graph processing, can be applied for the micro batches. However, a drawback of the micro-batch processing methodology is a high latency for detecting anomaly conditions and change points. this is because data are accumulated in a micro batch (e.g., 1 sec length) and then data analysis is performed for the micro batch. In this paper, we propose to offload one-at-a-time methodology analysis functions on an FPGA-based 10Gbit Ethernet network interface card (FPGA NIC) in cooperation with Spark Streaming framework, in order to significantly reduce the processing latency and improve the processing throughput. We implemented word count and change-point detection applications on Spark Streaming with our FPGA NIC, where a one-at-a-time methodology analysis logic is implemented. Experiment results demonstrates that the word count throughput is improved by 22x and the change-point detection latency is reduced by 94.12% compared to the original Spark Streaming. Our approach can complement the existing micro-batch methodology data analysis framework with ultra low latency one-at-a-time methodology logic.

关键词： field programmable gate arrays (FPGA)

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Packet processing on FPGA SoC with DPDK

Packet processing on FPGA SoC with DPDK

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international conference on field programmable logic and applications

作者： Jan Viktorin Jan Korenek Faculty of Information Technology Brno University of Technology Brno Czech Republic

One of the most important topics of today is a packet processing in data centers with respect to the power consumption and efficient utilization of computational resources. the ARM architecture has proved to be an energy efficient computational system. Together with an integrated FPGA on a single die, it offers potentially a high performance with respect to the power consumption. DPDK - a set of libraries and drivers intended primarily for fast packet processing - is becoming to be a standard approach for packet processing, especially in data centers. In this paper, we exploit the potential of packet processing based on DPDK and FPGA SoC architectures. Especially, we aim at the potential of utilizing the ARM Cortex-A9 and Cortex-A53 CPUs.

关键词： field programmable gate arrays Computer architecture throughput Process control Standards Power demand Linux

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Efficient processing of phased array radar in sense and avoid application using heterogeneous computing

Efficient processing of phased array radar in sense and avoi...

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international conference on field programmable logic and applications

作者： Luke Newmeyer Doran Wilde Brent Nelson Michael Wirthlin Department of Electrical and Computer Engineering Brigham Young University Provo Utah U.S.A.

this paper describes a tightly integrated phased-array radar platform for a UAV-based sense and avoid application. the system leverages heterogeneous computing on a Zynq 7000 SoC processor to efficiently process the large streams of radar data required to guide a small Unmanned Air Vehicle (UAV) away from obstacles and intruding air vehicles. the system is mounted on a small UAV which requires stringent size, weight, and power constraints, and thus data processing must be done efficiently. the system is implemented on the commercial MicroZed development board. Low-level radar data-stream processing is performed in the FPGA fabric on the Zynq, which accelerates processing and improves energy efficiency. the Zynq ARM CPUs are used to perform higher-level radar processing and avoidance algorithms. the final proof of concept system is 2.25 × 4 × 1.5 in 3 weighing only 120 g (0.26 lbs) and consumes 8 watts of power. As an example, the improvements demonstrated by executing the FFT algorithm in hardware will be highlighted where hardware FFT processing provides a 17× improvement in processing time and a 49× improvement in energy efficiency over a CPU only implementation on the same SoC.

关键词： Hardware field programmable gate arrays Unmanned aerial vehicles Phased arrays Radar applications Collision avoidance

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A survey on reconfigurable accelerators for cloud computing

A survey on reconfigurable accelerators for cloud computing

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international conference on field programmable logic and applications

作者： Christoforos Kachris Dimitrios Soudris Institute of Communication and Computer Systems (ICCS/NTUA) Athens Greece National Technical University of Athens (NTUA) Athens Greece

Data centers are experiencing an exponential increase in the amount of network traffic that they have to sustain due to cloud computing and several emerging web applications. To face this network load, large data centers are required with thousands of servers interconnected with high bandwidth switches. Current data center, based on general purpose processor, consume excessive power while their utilization is quite low. Hardware accelerators can provide high energy efficiency for many cloud applications but they lack the programming efficiency of processors. In the last few years, there several efforts for the efficient deployment of hardware accelerators in the data centers. this paper presents a thorough survey of the frameworks for the efficient utilization of the FPGAs in the data centers. Furthermore it presents the hardware accelerators that have been implemented for the most widely used cloud computing applications. Furthermore, the paper provides a qualitative categorization and comparison of the proposed schemes based on their main features such as speedup and energy efficiency.

关键词： Cloud computing field programmable gate arrays Hardware Data analysis Benchmark testing Sparks Measurement

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Single-FPGA, scalable, low-power, and high-quality 3D ultrasound beamformer

Single-FPGA, scalable, low-power, and high-quality 3D ultras...

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international conference on field programmable logic and applications

作者： W. Simon A. C. Yüzügüler A. Ibrahim F. Angiolini M. Arditi J.-P. thiran G. De Micheli École Polytechnique Fédérale de Lausanne (EPFL) Switzerland Department of Radiology University Hospital Center (CHUV) and University of Lausanne (UNIL) Switzerland

We present an efficient FPGA architecture suitable for a medical 3D ultrasound beamformer. We tackle the delay calculation bottleneck, which is the heart and the most critical part of the beamformer, by proposing a computationally efficient design that is able to perform volumetric real-time beamforming on a single-chip FPGA. the design has been demonstrated for a 32×32-channel receive probe, and we extrapolated the requirements of the architecture for 80×80 channels.

关键词： Delays field programmable gate arrays three-dimensional displays Computer architecture Imaging Ultrasonic imaging Probes

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Demonstration of a context-switch method for heterogeneous reconfigurable systems

Demonstration of a context-switch method for heterogeneous r...

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international conference on field programmable logic and applications

作者： Arief Wicaksana Alban Bourge Olivier Muller Frédéric Rousseau TIMA Laboratory - Grenoble-INP/UGA/CNRS Grenoble FRANCE

Nowadays, FPGAs are integrated in high-performance computing systems, servers, or even used as accelerators in System-on-Chip (SoC) platforms. Since the execution is performed in hardware, FPGA gives much higher performance and lower energy consumption compared to most microprocessor-based systems. However, the room to improve FPGA performance still exists, e.g. when it is used by multiple users. In multi-user approaches, FPGA resources are shared between several users. therefore, one must be able to interrupt a running circuit at any given time and continue the task at will. An image of the state of the running circuit (context) is saved during interruption and restored when the execution is continued. the ability to extract and restore the context is known as context-switch.

关键词： field programmable gate arrays Servers Context Interrupters Image restoration System-on-chip Hardware

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Overcoming resource underutilization in spatial CNN accelerators

Overcoming resource underutilization in spatial CNN accelera...

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international conference on field programmable logic and applications

作者： Yongming Shen Michael Ferdman Peter Milder Stony Brook University

Convolutional neural networks (CNNs) are revolutionizing a variety of machine learning tasks, but they present significant computational challenges. Recently, FPGA-based accelerators have been proposed to improve the speed and efficiency of CNNs. Current approaches construct an accelerator optimized to maximize the overall throughput of iteratively computing the CNN layers. However, this approach leads to dynamic resource underutilization because the same accelerator is used to compute CNN layers of radically varying dimensions. We present a new CNN accelerator design that improves the dynamic resource utilization. Using the same FPGA resources, we build multiple accelerators, each specialized for specific CNN layers. Our design achieves 1.3× higher throughput than the state of the art when evaluating the convolutional layers of the popular AlexNet CNN on a Xilinx Virtex-7 FPGA.

关键词： Digital signal processing field programmable gate arrays throughput Convolutional codes Image segmentation Dynamic scheduling Adders

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Modelling delay degradation due to NBTI in FPGA Look-up tables

Modelling delay degradation due to NBTI in FPGA Look-up tabl...

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international conference on field programmable logic and applications

作者： Mohammad Naouss François Marc University of Bordeaux IMS Laboratory Talence France

field-programmable Gate Arrays (FPGAs) benefit from the most advanced CMOS technology nodes, in order to meet the increasing demands of high performance and low power digital integrated circuits. this makes them susceptible to various reliability challenges at nano-scale. In this paper, we focus on aging degradation of the Look-up table (LUT) on FPGAs. We have characterized the delay degradation of LUT depending on the duty cycle of stress vectors. We have identified also that the duty cycle affects strongly the fall and moderately the rise delay of LUT due to the NBTI aging mechanism. Furthermore, a semi-empirical model of the degradation of LUT timing due to NBTI depending on the time and the duty cycle of stress vector has been investigated in this work. this model can be used to predict the degradation of a complex circuit implemented in a FPGA, and especially the risk of timing violations due to NBTI aging.

关键词： Delays Degradation Table lookup Stress field programmable gate arrays Aging Negative bias temperature instability

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