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检索条件"任意字段=17th International Conference on Field Programmable Logic and Applications"

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JetStream: An open-source high-performance PCI Express 3 streaming library for FPGA-to-Host and FPGA-to-FPGA communication

JetStream: An open-source high-performance PCI Express 3 str...

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international conference on field programmable logic and applications

作者： Malte Vesper Dirk Koch Kizheppatt Vipin Suhaib A. Fahmy School of Computer Science University of Manchester Mahindra École Centrale School of Engineering University of Warwick

Many FPGA-based accelerators are constrained by the available resources and multi-FPGA solutions can be necessary for building more capable systems. Available PCIe solutions provide only FPGA-to-Host communication. In this paper we present JetStream, an open-source 1 modular PCIe 3 library, supporting not only fast FPGA-to-Host communication, but also allowing direct FPGA-to-FPGA communication which fully bypasses the memory subsystem. the direct mode saves memory bandwidth for multicast modes and permits to connect multiple FPGAs in various software defined topologies. We show the benefits of JetStream with a large FIR filter spanning four FPGA boards, achieving throughputs of up to 7.09 GB/s per link. Utilizing direct FPGA-to-FPGA transfers reduces the required memory bandwidth by up to 75%.

关键词： field programmable gate arrays Registers Bandwidth Payloads throughput Engines Hardware

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Bayesian inference implemented on FPGA with stochastic bitstreams for an autonomous robot

Bayesian inference implemented on FPGA with stochastic bitst...

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international conference on field programmable logic and applications

作者： Hugo Fernandes M. Awais Aslam Jorge Lobo João Filipe Ferreira Jorge Dias ISR - Institute of Systems and Robotics University of Coimbra Portugal ISR - Institute of Systems and Robotics DEEC University of Coimbra Portugal DEEC Portugal Khalifa University Abu Dhabi UAE

this paper presents an FPGA implementation of a machine performing exact Bayesian inference using stochastic bitstreams. We revisited stochastic computing, not to perform better computations with unreliable hardware, but to perform approximate computations with less hardware. the underlying trade-off is between precision and computation time. An automatic design of probabilistic machines that compute soft inferences with an arithmetic based on stochastic bitstreams is presented. the computation tree provided by a Bayesian inference software is used to define the stochastic circuit. Tests were performed and results presented concerning accuracy and resource usage of the stochastic computing implementation of Bayesian machines performing exact inference. An application example is given of a Bayesian sensorimotor system that performs obstacle avoidance for an autonomous robot, fully implemented on an FPGA. Some conclusions were drawn on the followed approach, providing insights for future implementations.

关键词： Bayes methods Stochastic processes Robots field programmable gate arrays Computational modeling Probabilistic logic Probability distribution

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Accelerating recurrent neural networks in analytics servers: Comparison of FPGA, CPU, GPU, and ASIC

Accelerating recurrent neural networks in analytics servers:...

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international conference on field programmable logic and applications

作者： Eriko Nurvitadhi Jaewoong Sim David Sheffield Asit Mishra Srivatsan Krishnan Debbie Marr Intel Corporation

Recurrent neural networks (RNNs) provide state-of-the-art accuracy for performing analytics on datasets with sequence (e.g., language model). this paper studied a state-of-the-art RNN variant, Gated Recurrent Unit (GRU). We first proposed memoization optimization to avoid 3 out of the 6 dense matrix vector multiplications (SGEMVs) that are the majority of the computation in GRU. then, we study the opportunities to accelerate the remaining SGEMVs using FPGAs, in comparison to 14-nm ASIC, GPU, and multi-core CPU. Results show that FPGA provides superior performance/Watt over CPU and GPU because FPGA's on-chip BRAMs, hard DSPs, and reconfigurable fabric allow for efficiently extracting fine-grained parallelisms from small/medium size matrices used by GRU. Moreover, newer FPGAs with more DSPs, on-chip BRAMs, and higher frequency have the potential to narrow the FPGA-ASIC efficiency gap.

关键词： field programmable gate arrays Recurrent neural networks Graphics processing units Random access memory logic gates Classification algorithms Runtime

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Modeling considerations for the hardware-software co-design of flexible modern wireless transceivers

Modeling considerations for the hardware-software co-design ...

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international conference on field programmable logic and applications

作者： Benjamin Drozdenko Matthew Zimmermann Tuan Dao Kaushik Chowdhury Miriam Leeser School of Electrical and Computer Engineering Northeastern University Boston Massachusetts

Software-defined radios have introduced new platforms for dynamically modifying wireless system designs, and heterogeneous computing has opened up implementing such designs on different computing elements. Our goal is to develop a hardware-software modeling environment that captures reusability of various processing blocks at the physical layer for several modern protocols, and makes decisions regarding whether each processing block should be part of reconfigurable hardware or embedded processor software based on timing constraints and power budgets for the overlying applications. Our approach creates several different MathWorks Simulink model variants for both the transmitter and the receiver, each with a different boundary between hardware and software components. Using the 802.11a standard as an example, we use these models to generate a bitstream for the FPGA and executable code for the ARM processor on a Xilinx Zynq system-on-chip. Our results collect such metrics as data path delay, resource utilization, and power usage and demonstrate how to enhance the SDR design.

关键词： field programmable gate arrays Wireless communication Data models Hardware Software packages Delays

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Measure twice and cut once: Robust dynamic voltage scaling for FPGAs

Measure twice and cut once: Robust dynamic voltage scaling f...

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international conference on field programmable logic and applications

作者： Ibrahim Ahmed Shuze Zhao Olivier Trescases Vaughn Betz Department of Electrical and Computer Engineering University of Toronto Toronto ON Canada

Although dynamic voltage scaling (DVS) is a popular power reduction solution that has been widely used by processors and ASICs, it is still not commercially adopted by FPGAs. A unique feature of FPGAs that leads to challenges in adopting DVS is that the critical path and hence the minimum safe V dd depends on the configured application. We present a robust DVS technique that solves these challenges. For each application, we generate a calibration table (CT) that stores the actual failing points of that application on a specific FPGA, under various operating conditions. this CT is used to scale V dd while the application is running to guarantee safe operation with minimal power consumption. We develop an automated tool (FRoC) that ensures a Fast-Robust-Calibration of the FPGA to any application using it. FRoC ensures that the calibration process is invisible to FPGA users and does not add any extra manual steps to the design process. We show that our proposed DVS technique achieves a 33% total power reduction on two large applications.

关键词： field programmable gate arrays Voltage control Calibration Delays Testing Registers Temperature measurement

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Optimising Sparse Matrix Vector multiplication for large scale FEM problems on FPGA

Optimising Sparse Matrix Vector multiplication for large sca...

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international conference on field programmable logic and applications

作者： Paul Grigoraş Pavel Burovskiy Wayne Luk Spencer Sherwin Department of Computing Imperial College London Department of Aeronautics Imperial College London

Sparse Matrix Vector multiplication (SpMV) is an important kernel in many scientific applications. In this work we propose an architecture and an automated customisation method to detect and optimise the architecture for block diagonal sparse matrices. We evaluate the proposed approach in the context of the spectral/hp Finite Element Method, using the local matrix assembly approach. this problem leads to a large sparse system of linear equations with block diagonal matrix which is typically solved using an iterative method such as the Preconditioned Conjugate Gradient. the efficiency of the proposed architecture combined with the effectiveness of the proposed customisation method reduces BRAM resource utilisation by as much as 10 times, while achieving identical throughput with existing state of the art designs and requiring minimal development effort from the end user. In the context of the Finite Element Method, our approach enables the solution of larger problems than previously possible, enabling the applicability of FPGAs to more interesting HPC problems.

关键词： Sparse matrices field programmable gate arrays Computer architecture Finite element analysis Kernel Iterative methods Space exploration

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Time-borrowing platform in the Xilinx UltraScale+ family of FPGAs and MPSoCs

Time-borrowing platform in the Xilinx UltraScale+ family of ...

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international conference on field programmable logic and applications

作者： Ilya Ganusov Benjamin Devlin Xilinx Inc. San Jose CA

this paper presents enhancements to the Xilinx UltraScale+ clocking architecture to support fine-grain time-borrowing. Time borrowing improves performance by redistributing timing slack between fast and slow paths. the Ultra-Scale+ architecture introduces programmable hardware delays and pulse generators embedded in the clocking tree to support time-borrowing based both on clock skew scheduling and pulsed latches. this programmable hardware allows borrowing from a few picoseconds to multiple nanoseconds between sequential pipeline stages without any changes to RTL, placement or routing. Vivado algorithms automatically determine when to skew flip-flop clock or convert them to pulsed latches to achieve the highest possible performance. Using the default Vivado flow, this programmable time-borrowing platform delivers 5.5% F max increase on average over a suite of 89 industrial designs. It is especially effective on high-speed applications, delivering up to 13.7% F max increase on individual designs. We also demonstrate that using non-default features, such as delays cascades or increasing hold margin, can increase average performance gains to 7.4% and 8.5%, respectively. this platform incurs minimum area (less than 0.1% of total chip area) while staying robust in the presence of tight hold constraints and increasing process variation.

关键词： Clocks Latches Delays Pipelines field programmable gate arrays Routing

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Dimensionality reduction of hyperspectral images using reconfigurable hardware

Dimensionality reduction of hyperspectral images using recon...

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international conference on field programmable logic and applications

作者： Daniel Fenzández Carlos González Daniel Mozos Department of Computer Architecture and Automatics Complutense University of Madrid Madrid Spain

Remotely sensed hyperspectral imaging is a very active research area, with numerous contributions in the recent scientific literature. To carry out these investigations, it is necessary to collect large amounts of information that will be processed on satellite or airborne platforms using parallel processing techniques on multi core systems or Graphics Processing Units, trying to avoid excessive energy consumption. Due to the high dimensionality of the data, algorithms analyzing hyperspectral images have a high computational cost. this cost is a significant disadvantage in applications that require real-time response, such as fire tracing, prevention and monitoring of natural disasters, chemical spills and other environmental pollution, etc. To solve these problems, one of the solutions most used is the dimensional reduction, which removes noise and redundant information of images. therefore, it is possible to reduce significantly the size of the images, and improve the complexity of the algorithms and data storage. Moreover, field-programmable Gate Arrays are specially recommended in remotely sensed applications that require real-time response due to their features such as reconfiguration, low consumption, compact size and high computing power on board. In this work, we propose the implementation in reconfigurable hardware of the principal component analysis (PCA) algorithm to carry out the dimensional reduction of hyperspectral images. Experimental results demonstrate that our hardware version of the PCA algorithm exhibits real-time performance.

关键词： Principal component analysis Hyperspectral imaging field programmable gate arrays Covariance matrices Hardware Real-time systems

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EURECA compilation: Automatic optimisation of cycle-reconfigurable circuits

EURECA compilation: Automatic optimisation of cycle-reconfig...

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international conference on field programmable logic and applications

作者： Xinyu Niu Nicholas Ng Tomofumi Yuki Shaojun Wang Nobuko Yoshida Wayne Luk Dept. of Computing Imperial College London UK

EURECA architectures have been proposed as an enhancement to existing FPGAs, to enable cycle-by-cycle reconfiguration. applications with irregular data accesses, which previously cannot be efficiently supported in hardware, can be efficiently mapped into EURECA architectures. One major challenge to apply the EURECA architectures to practical applications is the intensive design efforts required to analyse and optimise cycle-reconfigurable operations, in order to obtain accurate and high-performance results while underlying circuits reconfigure cycle by cycle. this work proposes novel compiler support for EURECA-based designs. the compiler adopts (a) techniques based on session types to automatically derive a runtime reconfiguration scheduler that guarantees design correctness, and (b) a streaming circuit model to ensure high-performance circuits. three benchmark applications -large-scale sorting, Memcached, and Sparse Matrix Vector Multiplication (SpMV)- developed with the proposed compiler support show up to 11.2 times (21.8 times when architecture scales) reduction in area-delay product when compared with conventional architectures, and achieve up to 39% improvements compared with manually optimised EURECA designs.

关键词： Ports (Computers) Runtime Computer architecture Protocols Clocks field programmable gate arrays Kernel

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FMER: A hybrid configuration memory error recovery scheme for highly reliable FPGA SoCs

FMER: A hybrid configuration memory error recovery scheme fo...

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international conference on field programmable logic and applications

作者： Dimitris Agiakatsikas Ediz Cetin Oliver Diessel School of Computer Science and Engineering UNSW Australia School of Electrical Engineering and Telecommunications UNSW Australia

High-reliability SRAM-based field programmable Gate Array (FPGA) designs that are deployed in space are commonly triplicated to mask Single Event Upsets (SEUs) and employ either scrubbing or modular reconfiguration to recover from radiation-induced configuration memory errors. Scrubbing benefits from vendor support and clears errors anywhere in the design but suffers from longer recovery times and higher energy use. Module-based error recovery is more energy efficient and responsive but repairs only corrupted TMR modules, leaving the supporting parts of the design such as pins or routing that are not included in the modules unrecovered. this paper proposes and assesses a hybrid technique we refer to as Frame- and Module-based Error Recovery (FMER) that uses modular reconfiguration to repair faulty TMR modules and otherwise scrubs the supporting parts of the design. We derive and compare the reliability, availability and power consumption of TMR-based System on Chip (SoC) designs that incorporate FMER, modular reconfiguration alone, blind scrubbing and no recovery. Our results reveal that FMER has the highest reliability and availability of the studied techniques in high radiation environments or when a mission's energy budget is limited.

关键词： Tunneling magnetoresistance Reliability Energy consumption Pins field programmable gate arrays Maintenance engineering Markov processes

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