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DT-CGRA: Dual-track coarse-grained reconfigurable architecture for stream applications

DT-CGRA: Dual-track coarse-grained reconfigurable architectu...

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international conference on field programmable logic and applications

作者： Xitian Fan Huimin Li Wei Cao Lingli Wang State Key Laboratory of ASIC and System Fudan University Shanghai China

this paper presents a new type of coarse-grained reconfigurable architecture (CGRA) for the object inference domain in machine learning. the proposed CGRA is optimized for stream processing and a correspondent programming model called dual-track model is proposed. the CGRA is realized in Verilog HDL and implemented in SMIC 55 nm process, with the footprint of 3.79 mm 2 and consuming 1.79 W at 500 MHz. To evaluate the performance, eight machine-learning algorithms including HOG, CNN, k-means, PCA, SPM, linear-SVM, Softmax and Joint-Bayesian are selected as benchmarks. these algorithms cover a general machine learning flow in object inference domain: feature extraction, feature selection and inference. the experimental results show that the proposed CGRA can gain 1443× average energy efficiency comparing to the Intel i7-3770 CPU and 7.82× energy efficiency comparing to a high performance FPGA solution [19].

关键词： Kernel Programming Reconfigurable architectures Energy efficiency Context Arrays

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Effects of I/O routing through column interfaces in embedded FPGA fabrics

Effects of I/O routing through column interfaces in embedded...

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international conference on field programmable logic and applications

作者： Christophe Huriaux Olivier Sentieys Russell Tessier Inria IRISA Lannion France Department of Electrical and Computer Engineering University of Massachusetts Amherst MA

the emergence of 2.5D and 3D packaging technologies enables the integration of FPGA dice into more complex systems. Both heterogeneous manycore designs, which include an FPGA layer, and interposer-based multi-FPGA systems support the inclusion of reconfigurable hardware in 3D-stacked integrated circuits. In these architectures, the communication between FPGA dice or between FPGA and fixed-function layers often takes place through dedicated communication interfaces spread over the FPGA logic fabric, as opposed to an I/O ring around the fabric. In this paper, we investigate the effect of organizing FPGA fabric I/O into coarse-grained interface blocks distributed throughout the FPGA fabric. Specifically, we consider the quality of results for the placement and routing phases of the FPGA physical design flow. We evaluate the routing of I/O signals of large applications through dedicated interface blocks at various granularities in the logic fabric, and study its implications on the critical path delay of routed designs. We show that the impact of such I/O routing is limited and can improve chip routability and circuit delay in many cases.

关键词： field programmable gate arrays Fabrics Computer architecture Routing three-dimensional displays through-silicon vias Video recording

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High-level synthesis for medical image processing on Systems on Chip: A case study

High-level synthesis for medical image processing on Systems...

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international conference on field programmable logic and applications

作者： Fraser D Robinson Louise H Crockett William H Nailon Robert W Stewart Department of Biomedical Engineering University of Strathclyde Glasgow UK Department of Electronic and Electrical Engineering University of Strathclyde Glasgow UK Department of Oncology Physics Edinburgh Cancer Centre Edinburgh UK

Adaptive radiotherapy is a technique intended to increase the accuracy of radiotherapy. Currently, it is not clinically feasible due to the time required to process the images of patient anatomy. Hardware acceleration of image processing algorithms may allow them to be carried out in a clinically acceptable timeframe. this paper presents the experiences encountered using high-level synthesis tools to design an accelerated segmentation algorithm for computed tomography images targeted for implementation on a System on Chip. Hardware coprocessors and their interfaces for optimal threshold generation and 3D mean filter algorithms were synthesised from C++ functions. Hardware acceleration significantly outperformed the software only implementation. the high-level synthesis tools allowed the rapid exploration of different design options. However, hardware design knowledge was still necessary in order to interpret the results effectively.

关键词： Hardware Algorithm design and analysis Acceleration Software algorithms Software Coprocessors field programmable gate arrays

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Fast and robust hashing for database operators

Fast and robust hashing for database operators

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international conference on field programmable logic and applications

作者： Kaan Kara Gustavo Alonso Dept. of Computer Science ETH Zurich Switzerland

Hashing is an essential part of many database operators, such as joins or aggregation, especially when executed in parallel. Often, database engines resort to using easily computed hash functions like modulo to prevent that hashing becomes a bottleneck. the disadvantage of simple hash functions is that they produce imperfect data distributions, particularly when the data is skewed. Robust hash functions produce balanced distributions but they are computationally expensive. Our purpose in this paper is to break the present trade-off between robustness and performance. We achieve this by showing how to implement robust hash functions suitable for database operators on an FPGA. Our target platform (Intel QuickAssist QPI-FPGA) provides a shared memory architecture between the CPU and the FPGA, enabling database engines to use the hardware hashing without any modifications to their memory layout. Depending on the hash function, we achieve 6.6× improvement over pure software implementations. We also show how to integrate hardware hashing in a hybrid hash table without any acceleration overhead.

关键词： field programmable gate arrays Hardware Software Robustness Databases Acceleration Computer architecture

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TeSHoP: A Temperature Sensing based Hotspot-Driven Placement technique for FPGAs

TeSHoP: A Temperature Sensing based Hotspot-Driven Placement...

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international conference on field programmable logic and applications

作者： Weina Lu Yu Hu Jing Ye Xiaowei Li Graduate University of Chinese Academy of Sciences Chinese Academy of Sciences Institute of Computing Technology

the rapid shrinking of the feature size in CMOS technology has significantly increased the power density of integrated circuits, leading to excessive temperature. though online thermal management techniques such as DVFS and task migration can mitigate the temperature issue, but usually incur significant performance penalty. therefore, it is crucial to optimize temperature at the design stage. In this work, we propose the TeSHoP, a Temperature Sensing based Hotspot-Driven Placement technique for FPGAs. Firstly, the un-optimized circuit along with a sensor network is run in FPGA to obtain the real temperature profile of the circuit. then, based on the temperature profile, we proceed a one-off adjustment of the circuit placement for hotspot optimization. the optimization is modeled as a Hyper Minimum Bipartite Matching problem for solving. We implement the whole optimization flow in a real FPGA, with extension of the VTR-to-Bitstream tool. Experimental results on Xilinx Virtex-6 FPGA show that the reduction of peak temperature and the improvement of thermal uniformity can be up to 7.5°C and 13.9% respectively.

关键词： Temperature sensors field programmable gate arrays Optimization Temperature measurement Benchmark testing Routing

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Trojans modifying soft-processor instruction sequences embedded in FPGA bitstreams

Trojans modifying soft-processor instruction sequences embed...

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international conference on field programmable logic and applications

作者： Ismail San Nicole Fern Cetin Kaya Koc Kwang-Ting Cheng University of California Santa Barbara CA USA Anadolu University Eskisehir Turkey

Reconfigurable platforms such as FPGAs and CPLDs are used to implement flexible and lightweight embedded systems often using soft-processors and a fixed instruction sequence stored in block memories. the bitstream format is proprietary for most vendors, however, in this work we demonstrate how to identify and extract block memory contents within the bitstream, allowing an adversary to learn and possibly modify the fixed instruction sequence. Manipulating the instruction sequence by inserting a Trojan in the bitstream as opposed to in the RTL code allows an adversary to bypass many verification steps. Moreover, the proposed Trojans only add extra instructions to the sequence to leak secret information, and do not change the original program behavior, making them virtually impossible to detect using functional tests. We present a case study where a Trojan is injected into a MIPS AES encryption program to leak internal state information by adding extra instructions from the available ones without changing the original program behavior.

关键词： field programmable gate arrays Decoding Trojan horses Encryption Embedded systems Algorithm design and analysis

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Search-based synthesis of approximate circuits implemented into FPGAs

Search-based synthesis of approximate circuits implemented i...

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international conference on field programmable logic and applications

作者： Zdenek Vasicek Lukas Sekanina Faculty of Information Technology IT4Innovations Centre of Excellence Brno Czech Republic

Approximate computing is capable of exploiting the error resilience of various applications with the aim of improving their parameters such as performance, energy consumption and area on a chip. In this paper, a new systematic approach for the approximation and optimization of circuits intended for LUT-based field programmable gate arrays (FPGAs) is proposed. In order to deliver a good trade-off between the quality of processing and implementation cost, the method employs a genetic programming-based optimization engine. the circuits are internally represented and optimized at the gate level. the resulting LUT-based netlists are obtained using a commercial FPGA tool. In the experimental part, four commonly available commercial FPGA design tools (Xilinx ISE, Xilinx Vivado, Precision, and Quartus) and state-of-the-art academia circuit synthesis and optimization tool ABC are compared. the quality of approximated circuits is evaluated using relaxed equivalence checking by means of Binary decision diagrams. An important conclusion is that the improvements (i.e. area reductions) at the gate level are preserved by the FPGA design tools and thus the number of LUTs is also adequately reduced. It was shown that the current state-of-the-art synthesis tools provide (for some instances) the results that are far from an optimum. For example, a 40% reduction (68 LUTs) was achieved for `clmb' benchmark circuit (Bus Interface) without introducing any error. Additional 43% reduction can be obtained by introducing only a 0.1% error.

关键词： logic gates field programmable gate arrays Table lookup Optimization Boolean functions Design tools

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SoCLog: A real-time, automatically generated logging and profiling mechanism for FPGA-based Systems On Chip

SoCLog: A real-time, automatically generated logging and pro...

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international conference on field programmable logic and applications

作者： Ioannis Parnassos Panagiotis Skrimponis Georgios Zindros Nikolaos Bellas Center for Research & Technology Hellas (CERTH) University of Thessaly Greece

Recent advances in FPGA technology and the proliferation of High Level Synthesis (HLS) tools makes it possible to implement complex System on Chip (SoC) designs that realize complete applications in a single FPGA device. To be able to exploit the large performance vs. area search space of such modern FPGA-based SoCs, system architects must have the appropriate performance analysis tools to evaluate-preferably at runtime-the computational requirements and the data flow of such a system to determine potential performance bottlenecks when running realistic workloads. In this paper we introduce SoCLog, a framework that automatically enhances the platform architecture with additional hardware components used to generate activity logs when the base SoC architecture executes an application. this real-time information can be analyzed by the system designer to expose performance bottlenecks not only on aggregate, but also at clock cycle granularity thus revealing potential design inefficiencies when there is burst of activity in the system. We evaluate our framework with a number of SoC designs to show that such a logging information can be valuable for the design of a complex SoC in a modern FPGA with minimal area overhead.

关键词： Hardware field programmable gate arrays Discrete cosine transforms Computer architecture Kernel Benchmark testing

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Optimal random sampling based path planning on FPGAs

Optimal random sampling based path planning on FPGAs

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international conference on field programmable logic and applications

作者： Size Xiao Adam Postula Neil Bergmann School of Information Technology and Electrical Engineering The University of Queensland Australia

Random sampling based path planning algorithms have shown their high efficiency in robotics, navigation and related fields. the Rapidly-Exploring Random Trees (RRT) is the typical method and works well in a variety of applications. Due to the sub-optimal issue of original RRT, the recent algorithm, known as RRT*, significantly improves the optimality of solution by adding the “cost review” procedure. However, the original RRT experiences the bottle neck of complicated iterations and it becomes worse in RRT*. this paper presents the developed hardware architecture for RRT*, which fully exploits the parallel potential of algorithm. Unlike the sequential execution in software, the “exploration” and “review” are identified as independent processes and executed in parallel. For the complicated operation of inserting vertexes, one pipelined Kd-tree constructor is designed to fast rebuild the tree when new vertex generated. Furthermore, to speed up the near neighbors and nearest neighbor searching, the vertexes are stored in separate Kd-trees so that the search processes can be carried out concurrently in each data tree. this work explores the possible and power-efficient RRT* hardware architecture on FPGAs compared to PC implementation.

关键词： Algorithm design and analysis Hardware Computer architecture Acceleration Sorting Path planning field programmable gate arrays

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Accelerating a charged single α-helix search algorithm in protein sequences using FPGA 15

Accelerating a charged single α-helix search algorithm in p...

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15th international Workshop on Cellular Nanoscale Networks and their applications, CNNA 2016

作者： Nagy, Zoltán Gáspári, Zoltán Kovács, Ákos Faculty of Information Technology Pázmány Péter Catholic University Práter u. 50/A. BudapestH-1083 Hungary Cellular Sensory and Optical Wave Computing Laboratory Hungarian Academy of Sciences Kende u. 13-17. BudapestH-1111 Hungary

ISBN: (纸本)9783800742523

Processing and analyzing the immense amount of biological data generated each day requires fast and accurate bioinformatics algorithms. the main characteristic of the these algorithms is the low precision input data which can be stored on 2-5bits. therefore reconfigurable architectures can be used more efficiently compared to conventional 32 or 64 bit microprocessors, because the accuracy of the functional units can be customized and a relatively small amount of configurable logic is required. In the paper a new architecture is introduced and implemented on FPGA to speed-up a structural motif search algorithm. the architecture can be implemented on a versatile medium range FPGA providing about two orders of magnitude speedup. the system can be efficiently scaled to process several sequences in parallel on a larger FPGA resulting in even higher speedup. © VDE VERLAG GMBH.

关键词： field programmable gate arrays (FPGA)

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