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Implementation of efficient portable low delay adder using FPGA

Implementation of efficient portable low delay adder using F...

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international conference on Microelectronics, ICM

作者： Mohamed Barakat Waleed Saad Mona Shokair Mohamed Elkordy CCE department Nhada University Egypt ECE department Menofia University Egypt

No doubt that in this technological era the arithmetic circuit is the core of most all the Digital Signal Processing applications (DSP), especially adder circuits. In this paper, various types of adder circuits have been implemented on field programmable Gate Array (FPGA). Furthermore, another architecture for adder called Carry Shifting Adder (CSHA) is proposed. this depends on shifting the carry to the next stage. then it's combined with a carry increment circuit to get a low delay. the goal of this paper is to efficiently carry out the proposed CSHA adder with carry increment circuit over FPGA kit. Simulations are done to find out the circuit area and delay. Also, this is compared with the related other adder circuits. the performance of this proposed adder circuit is better than other related ones in both area and delay.

关键词： Adders Delays field programmable gate arrays Multiplexing logic gates Integrated circuit modeling Simulation

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Significant Papers from the First 25 Years of the FPL conference 25

Significant Papers from the First 25 Years of the FPL Confer...

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25th international conference on field programmable logic and applications

作者： Leong, Philip H. W. Amano, Hideharu Anderson, Jason Bertels, Koen Cardoso, Joao M. P. Diessel, Oliver Gogniat, Guy Hutton, Mike Lee, JunKyu Luk, Wayne Lysaght, Patrick Platzner, Marco Prasanna, Viktor K. Rissa, Tero Silvano, Cristina So, Hayden Wang, Yu Univ Sydney Sydney NSW 2006 Australia Keio Univ Tokyo 108 Japan Univ Toronto Toronto ON M5S 1A1 Canada Delft Univ Technol NL-2600 AA Delft Netherlands Univ Porto P-4100 Oporto Portugal Univ NSW Kensington NSW Australia Univ South Brittany Lorient France Altera Corp San Jose CA USA Imperial Coll London London England Xilinx Res Labs San Jose CA USA Univ Paderborn Paderborn Germany Univ Southern Calif Los Angeles CA USA Nokia Espoo Finland Politecn Milan Milan Italy Univ Hong Kong Hong Kong Hong Kong Peoples R China Tsinghua Univ Beijing Peoples R China

the list of significant papers from the first 25 years of the field-programmable logic and applications conference (FPL) is presented in this paper. these 27 papers represent those which have most strongly influenced ...

ISBN: (纸本)9781467381239

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Hybrid FPGA debug approach 25

Hybrid FPGA debug approach

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25th international conference on field programmable logic and applications

作者： Panjkov, Zdravko Wasserbauer, Andreas Ostermann, Timm Hagelauer, Richard Intel Mobile Commun Danube Mobile Commun Engn Linz Austria Johannes Kepler Univ Linz Inst Integrated Circuits Linz Austria

ISBN: (纸本)9781467381239

In the modern verification environment an FPGA-based prototyping has become an important part of the whole verification flow. the ability to simulate real time application in more realistic speeds allows much higher coverage than traditional HDL logic simulators. the main disadvantage of FPGA prototyping is inability to inspect and observe internal FPGA signals. Currently there are two traditional solutions for this problem. the first solution is using embedded trace-buffers to record a subset of internal signals and the second solution captures a snapshot of the current FPGA state. Both of these techniques have certain benefits and shortcomings. In this paper, we present an idea of merging these two techniques into a new hybrid approach. Using this idea we created a hybrid circuit and during our experiments showed that it preserves all good sides from both traditional approaches.

关键词： Hybrid Circuit Device Component field programmable gate arrays debugger Snapshots PROBLEM SOLUTION international Data Encryption Algorithm real-time application program PROTOTYPE

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ParaLaR: A Parallel FPGA router based on Lagrangian Relaxation 25

ParaLaR: A Parallel FPGA router based on Lagrangian Relaxati...

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25th international conference on field programmable logic and applications

作者： Hoo, Chin Hau Kumar, Akash Ha, Yajun Natl Univ Singapore Dept Elect & Comp Engn Singapore Singapore

ISBN: (纸本)9781467381239

Routing of nets is one of the most time consuming steps in the FPGA design flow. While existing works have described ways of accelerating the process through parallelization, they are not scalable. In this paper, we propose a scalable way of parallelizing the routing algorithm through Lagrangian relaxation. the FPGA routing problem is formulated as a linear programming problem, and the channel width constraints, which limit the amount of parallelism, are relaxed by incorporating them into the objective function. the result of the relaxation yields independent sub-problems that we solve using minimum Steiner tree algorithms. Our approach outperforms the state-of-the-art FPGA parallel router by producing an average self-relative speedup of 7.05X with 8 threads, reduces the total wire length by 22.4% on average and has similar channel width requirements as VPR, albeit at the cost of 7.5% longer critical path. Another advantage of our algorithm is that the number of threads and the order in which the nets are routed has totally no impact on the quality of result.

关键词： field programmable gate arrays (FPGA)

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Compact Dual Block AES core on FPGA for CCM Protocol 25

Compact Dual Block AES core on FPGA for CCM Protocol

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25th international conference on field programmable logic and applications

作者： Resende, Joao Carlos Chaves, Ricardo Univ Lisbon Inst Super Tecn INESC ID Rua Alves Redol 9 P-1000029 Lisbon Portugal

ISBN: (纸本)9781467381239

this paper presents a compact and FPGA based implementation of the AES encryption standard, specifically designed for processing two independent 128-bit input blocks in feedback modes. this configuration is particularly focused on the Counter with CBC-MAC Protocol, but can also be adapted to other AES based encryption-authentication protocols requiring the processing of two independent data streams. Most of the state of the art solutions implementing CCMP consider large datapaths, sometimes with separated encryption datapaths for the different data streams, leading to low resource efficiency. the work herein proposed suggests that with adequate FPGA component usage and with proper data scheduling a very compact and efficient dual AES core can be derived particularly on FPGAs. Overall, the proposed structure allows for a throughput of 1.7Gbps while achieving a throughput/Slice efficiency of 24.22 Mbps/Slice, 47% higher than the existing related state of the art.

关键词： field programmable gate arrays (FPGA)

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Generating FPGA Accelerators for Chemical Similarity Assessment 25

Generating FPGA Accelerators for Chemical Similarity Assessm...

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25th international conference on field programmable logic and applications

作者： Alachiotis, Nikolaos Carnegie Mellon Univ Dept Elect & Comp Engn Pittsburgh PA 15217 USA

ISBN: (纸本)9781467381239

Numerical measures of similarity/distance between objects represented by binary vectors are common in a wide range of disciplines. Searching in large-scale chemical databases requires billions of comparisons between molecules that are represented by binary fingerprints to capture the atomic structure. the performance bottleneck here is the enumeration of set bits in vectors (population count). Due to the discrete representation, similarity measures between binary fingerprints should fit well to FPGAs. We present an architecture to accelerate binary similarity assessment, evaluate various design points, and compare performance to highly optimized CPU and GPU implementations. We implement an RTL generation software, SimGenRTL, to generate accelerators of various sizes based on the proposed architecture. We find that accelerators with fewer and wider population counters allow better distribution of the hardware resources, outperforming significantly accelerators with more and narrower bit-enumeration components. SimGenRTL is available for download to allow rapid design space exploration of the computational core ahead of a full custom system implementation.

关键词： field programmable gate arrays (FPGA)

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Single-FPGA 3D ultrasound beamformer

Single-FPGA 3D ultrasound beamformer

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international conference on field programmable logic and applications

作者： A. C. Yüzügüler W. Simon A. Ibrahim F. Angiolini M. Arditi J.-P. thiran G. De Micheli École Poly technique Fédérale de Lausanne (EPFL) Switzerland Department of Radiology University Hospital Center (CHUV) and University of Lausanne (UNIL) Switzerland

In medical diagnosis, ultrasound (US) imaging is one of the most common, safe, and powerful techniques. Volumetric (3D) US imaging, an emerging technique, is even more attractive than standard 2D imaging, as it allows for imaging without the local presence of a trained sonographer finely positioning the probe. this would be particularly useful in rescue operations, remote areas and developing countries. Unfortunately, present-day 3D imagers are expensive, bulky and power-hungry, confining them to hospitals. there is therefore a strong motivation to develop efficient electronics to enable a portable US platform that is small, cheap, and battery-operated. Beamforming (BF) is the most computationally expensive of 3D imaging. Both commercial [1] and research [2] imagers have dealt with the challenge by reducing the number of receive channels, hence simplifying the computation through the usage of far fewer elements. this comes at the cost of image quality, and the resulting machines are nonetheless still non-portable and expensive. In turn, the bottleneck of the BF process is the calculation of acoustic delays, which requires up to trillions of square roots per second. We propose a drastically more efficient architecture [3]. With geometric considerations, each delay is calculated from a small set of square roots (mapped onto CORDICs), plus two additions. In this demo, we will show the reconstruction of a 2.5M-voxel volume, supporting a transducer with 32×32 receive channels. We have fitted the architecture into a single Kintex UltraScale KU040 [4], which is unprecedented. We also extrapolated the utilization of a 80×80 instance on a Virtex UltraScale XCVU190 [4]. Table I shows the implementation results. Fig. 1 shows our beamformer custom block connected to the other FPGA subsystems. the delay calculation architecture is shown in Fig. 2. the demo setup is presented in Fig. 3, where the 3D beamformer is implemented on the FPGA, while the pre- and post-processing stages

关键词： Delays three-dimensional displays field programmable gate arrays Ultrasonic imaging Imaging Table lookup

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FPGA-based All-digital Software Defined Radio Receiver 25

FPGA-based All-digital Software Defined Radio Receiver

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25th international conference on field programmable logic and applications

作者： Prata, Andre Oliveira, Arnaldo S. R. Carvalho, Nuno Borges Univ Aveiro DETI Inst Telecomunicacoes Aveiro Portugal

ISBN: (纸本)9781467381239

In this Ph.D. work it is intended to explore innovative agile and wideband FPGA-based Software Defined Radio (SDR) receiver architectures for future 5G wireless communications. this short paper presents some preliminary work in this area, including interesting results of an innovative SDR receiver. this new architecture implements the analog-to-digital conversion directly at RF stage based on Pulse Width Modulation (PWM). the system is implemented using the high speed differential input buffers of a medium range FPGA as a comparator. Simulation and measured results will be presented and evaluated in terms of Signal-to-Noise Ratio (SNR) and Error Vector Magnitude (EVM). Briefly, this architecture allows an input bandwidth of almost 3GHz maintaining an EVM below 2% for a 2MHz wide signal.

关键词： field programmable gate arrays Software radio radio receivers Receivers Pulse width modulation SDPR gene signal to noise ratios

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Fast FPGA System for Microarchitecture Optimization on Synthesizable Modern Processor Design 25

Fast FPGA System for Microarchitecture Optimization on Synth...

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25th international conference on field programmable logic and applications

作者： Huang, Libo Wang, Yongwen Dou, Qiang Zhang, Chengyi Sun, Caixia Xu, Chao Natl Univ Def Technol Sch Comp Changsha 410073 Hunan Peoples R China

ISBN: (纸本)9781467381239

Microarchitecture optimization for processor design is a must to achieve target system performance. Provided the register transfer level (RTL) model in real chip design, this paper proposes MOFPGA system, which uses field programmable gate array (FPGA) prototyping as an effective method for fine-grain microarchitecture optimization. It is a fast, reconfigurable, and visible platform with zero impact on the performance of the monitored processor. MOFPGA implements a complete computing platform equipped with a modern out-of-order processor and is able to achieve 60 MHz processor frequency. Besides general FPGA implementation techniques such as multi-port SRAM design and gate-clock conversion, extensive optimization efforts are done to improve the FPGA performance of mapping such a large core. To our knowledge, MOFPGA is the first published FPGA system that implements a modern out-of-order processor running at such high frequency and can report the real SPEC CPU2000 evaluation results.

关键词： field programmable gate arrays (FPGA)

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Characterisation of Feasibility Regions in FPGAs under Adaptive DVFS 25

Characterisation of Feasibility Regions in FPGAs under Adapt...

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25th international conference on field programmable logic and applications

作者： Dahir, Nizar Campos, Pedro Tempesti, Gianluca Trefzer, Martin Tyrrell, Andrew Univ York Dept Elect York YO10 5DD N Yorkshire England

ISBN: (纸本)9781467381239

Implementing Dynamic Voltage and Frequency Scaling (DVFS) is a non-trivial task on FPGAs and requires knowledge about the feasible voltage and frequency (VF) ranges as a first step. the VF feasible ranges depend not only on the size of the critical path in the design but also on the inter-and intra-die variability on the FPGA die. Moreover, the variations in the configuration of the FPGA highly affect feasible VF ranges. therefore, it is crucial to characterise feasibility by studying the relationship between feasible VF regions and these sources of variability in FPGAs. In this paper we employ a self-checking multiplier which uses residue codes and DVFS implemented on the programmable logic component of a Xilinx Zynq ZC702 device as an error-detection circuit to study these feasible regions. Results show that, as expected, feasible VF ranges vary with FPGA configuration. More interestingly, significant variation of the feasible VF regions is found for different dies. these results highlight the necessity of dynamic self-testing as a part of an adaptive DVFS implementation on FPGAs. Employing the techniques presented in this work enables the implementation of efficient adaptive on-line DVFS on programmable logic while ensuring reliability.

关键词： field programmable gate arrays residue codes Self tuning Multiplying circuits programmable dies

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