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Static Hardware Task Placement on Multi-Context FPGA Using Hybrid Genetic Algorithm 25

Static Hardware Task Placement on Multi-Context FPGA Using H...

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25th international conference on field programmable logic and applications

作者： Liang, Hao Sinha, Sharad Warrier, Rakesh Zhang, Wei Hong Kong Univ Sci & Technol Dept Elect & Comp Engn Hong Kong Hong Kong Peoples R China Nanyang Technol Univ Sch Comp Engn Singapore Singapore

ISBN: (纸本)9781467381239

field programmable Gate Arrays (FPGAs) are becoming pervasive in various kinds of computationally demanding applications. Working in a tightly coupled processor-coprocessor architecture, FPGAs are often anticipated to accelerate multiple fine-grained or coarse-grained tasks simultaneously. Single-context FPGAs are commonly used in such systems. With the recent development of emerging memory technologies, multicontext FPGAs that support dynamic reconfiguration with high-density non-volatile memories become feasible. Compared to single-context FPGAs, multi-context FPGAs are able to accelerate significantly more tasks with only moderate area and power overhead. However, the best way to utilize the computation capacity advantage of multi-context FPGAs for hardware task mapping remains an interesting and unexploited problem. In this paper, we first propose the framework of a processor-coprocessor architecture with multi-context FPGA as the coprocessor for multiple-task acceleration. Under the framework, a hybrid placement strategy based on genetic and greedy algorithms is proposed to efficiently place a set of tasks onto the multi-context FPGA to achieve the best logic capacity utilization. Experiments on real and synthetic benchmarks demonstrate the efficiency of the proposed algorithm compared with other general approaches.

关键词： field programmable gate arrays (FPGA)

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A Technology Mapper for Depth-Constrained FPGA logic Cells 25

A Technology Mapper for Depth-Constrained FPGA Logic Cells

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25th international conference on field programmable logic and applications

作者： Jiang, Zhenghong Zgheib, Grace Lin, Colin Yu Novo, David Huang, Zhihong Yang, Liqun Yang, Haigang Ienne, Paolo Chinese Acad Sci Inst Elect Syst Programmable Chip Res Dept Beijing Peoples R China Ecole Polytech Fed Lausanne Sch Comp & Commun Sci CH-1015 Lausanne Switzerland

ISBN: (纸本)9781467381239

In the last decade, progress in logic synthesis has brought about new advantageous circuit representations. these representations, such as And-Inverter Graphs in the ubiquitous open-source synthesizer ABC, have inspired new designs of field programmable Gate Arrays (FPGAs), which, instead of using Look-Up Tables (LUTs), mimic the topology of the circuit representation in the basic logic cells. More recent examples are Majority-Inverter Graphs, another uniform representation which has triggered considerable interest in synthesis and which naturally suggests new logic cells. Yet, in this paper we observe how naively adapting technology mapping solutions for classic LUT-based FPGAs to these new architectures incurs severe shortcomings. the key issue is that LUTs are inherently input-constrained (the logic function they implement is irrelevant) and have generally a single output;on the other hand, logic cells made of uniform networks of some fundamental logic function (e.g., And-Invert) are constrained in terms of logic depth and multiple outputs are an integral feature. We introduce novel and effective solutions to address these differences;the result is a highly versatile mapper-thus enabling further research in these new architectures-with a significantly better performance than what is described in literature for one such architecture. Specifically, when we compare with the state of the art on one sample architecture, we obtain a significant decrease in area (on average 18% over several benchmarks) while also improving slightly the critical path (a reduction of 3%).

关键词： field programmable gate arrays (FPGA)

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A portable open-source controller for safe Dynamic Partial Reconfiguration on Xilinx FPGAs 25

A portable open-source controller for safe Dynamic Partial R...

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25th international conference on field programmable logic and applications

作者： Di Carlo, Stefano Prinetto, Paolo Trotta, Pascal Andersson, Jan Politecn Torino Dip Automat & Informat Turin Italy Cobham Gaisler AB Gothenburg Sweden

ISBN: (纸本)9781467381239

thanks to their flexibility, increasing performances and low Non-Recurrent Engineering costs, SRAM-based field programmable Gate Array (FPGA) devices often represent the preferred platforms for the final deployment of highly reliable systems. In this context, Dynamic Partial Reconfiguration (DPR) is far from being widely adopted due to the additional complexity introduced during the hardware design phase, and the dependability issues related to the FPGA reconfiguration process itself. this paper presents a portable open-source controller for safely enabling self dynamic and partial reconfiguration of systems implemented on Xilinx FPGAs. the controller embeds configurable error detection and correction circuitry that enables a safe DPR by monitoring for partial bitstreams data errors. Experiments highlight the high performances achieved and the limited hardware resources needed to implement it on different devices. the HDL source code has been made available through the popular open-source Cobham Gaisler GRLIB IP-cores library.(1)

关键词： hardware resource Reconfiguration field programmable gate arrays open source HIGH-PERFORMANCE Controllers error detection and correction dial pulse receiver

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Enabling Seamless Execution on Hybrid CPU/FPGA Systems: Challenges & Directions 25

Enabling Seamless Execution on Hybrid CPU/FPGA Systems: Chal...

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25th international conference on field programmable logic and applications

作者： Belwal, Meena Purnaprajna, Madhura Sudarshan, T. S. B. Amrita Vishwavidya Peetham Amrita Univ Amrita Sch Engn Dept Comp Sci & Engn Bangalore Karnataka India

ISBN: (纸本)9781467381239

Today's computing systems are heterogeneous, with diverse micro-architectures. It is common to design systems comprising multi-core CPUs, Digital Signal Processors (DSP) and Graphic Processing Units (GPUs). In addition to these devices, the extensive configurability and parallelism in field programmable Gate Arrays (FPGAs) has proven to be advantageous for accelerating complex computational problems. In comparison to CPUs, DSPs and GPUs, FPGAs have a distinctly different microarchitecture. In this context, enabling seamless application execution in a system composed of FPGAs alongside CPUs, is a major challenge. As a consequence, simplifying programmability of hybrid CPU/FPGA systems demands innovations in system software support. there has been research in extending the traditional CPU-only system techniques to CPU/FPGA based hybrid systems to make way for FPGA-based mainstream computing. this article surveys techniques in dynamic task management aimed at reducing or completely eliminating the burden of operating system writers for CPU/FPGA hybrid systems and provide insight to researchers to explore further.

关键词： central processing units field programmable gate arrays hybrid systems task processing Systems software parallelism Technological Innovations Legal Executions Enabling Insight

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Estimating Circuit Delays in FPGAs after Technology Mapping 25

Estimating Circuit Delays in FPGAs after Technology Mapping

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25th international conference on field programmable logic and applications

作者： Severens, Berg Vansteenkiste, Elias Heyse, Karel Stroobandt, Dirk Univ Ghent Dept Elect & Informat Syst Comp Syst Lab Hardware & Embedded Syst Team B-9000 Ghent Belgium

ISBN: (纸本)9781467381239

An FPGA implementation requires a significant effort of the hardware designer, who optimizes FPGA designs by going through many time-consuming CAD flow iterations. these iterations provide two types of feedback: (1) the FPGA performance and (2) the identification of the parts having the highest impact on the FPGA performance. Both depend on the wirelength behavior. Studies have been dedicated to the estimation of local [5] and global [4] wirelengths, but to our knowledge both performance estimations and identification of the critical zone are not present in literature. therefore this paper, firstly, presents a comparison of three performance estimation techniques: logic depth, Monte Carlo simulation and fast placement (ordered from low to high accuracy and runtime). Secondly, four methods identifying the critical zone are compared. Results show that Monte Carlo simulations provide a good identification of the parts having the highest impact on the performance. We conclude that Monte Carlo simulations provide useful feedback within a short runtime (about 30 times faster than placement), reducing the time-tomarket of FPGA implementations.

关键词： field programmable gate arrays critical zone Monte Carlo technique Performance Evaluation Runtime placement HIGH IMPACT iterative methods IMPACT PROPERTIES

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Accurate Power Analysis for Near-V_t RRAM-based FPGA 25

Accurate Power Analysis for Near-<i>V<sub>t</sub></i> RRAM-b...

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25th international conference on field programmable logic and applications

作者： Tang, Xifan Gaillardon, Pierre-Emmanuel De Micheli, Giovanni Ecole Polytech Fed Lausanne Lausanne Switzerland

ISBN: (纸本)9781467381239

Resistive Random Access Memory (RRAM)-based FPGA architectures employ RRAMs not only as memories to store the configuration but embed them in the datapaths of programmable routing resources to propagate signals with improved performances. Sources of power consumption have been intensively studied for conventional Static Random Access Memories (SRAM)-based FPGAs. However, very limited works focused so far on studying the power characteristics of RRAM-based FPGAs. In this paper, we first analyze the power characteristics of RRAM-based multiplexer at circuit level and then use electrical simulations to study power consumption of RRAM-based FPGA architectures. Experimental results show that RRAM-based FPGAs achieve a Power-Delay Product reduced by 50% compared to SRAM-based FPGA at nominal voltage and 20% compared to near-V-t SRAM-based FPGA, respectively.

关键词： field programmable gate arrays (FPGA)

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POWER-EFFICIENT RANGE-MATCH-BASED PACKET CLASSIFICATION ON FPGA 25

POWER-EFFICIENT RANGE-MATCH-BASED PACKET CLASSIFICATION ON F...

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25th international conference on field programmable logic and applications

作者： Qu, Yun R. Prasanna, Viktor K. Univ Southern Calif Ming Hsieh Dept Elect Engn Los Angeles CA 90089 USA

ISBN: (纸本)9781467381239

Packet classification is a kernel application performed at network routers. Many classification engines are optimized for prefix and exact match, while a range-to-prefix translation can lead to rule set expansion. Under limited power budget, it is challenging to achieve high classification throughput. In this paper, we present a high-performance and power-efficient packet classification engine on FPGA. We construct a modular Processing Element ( PE);each PE compares a stride of the input packet header against a stride of a range boundary. We concatenate multiple PEs into a systolic array. Efficient power optimization techniques including self-enabled power gating and entropy-based scheduling are explored on our architecture. Experimental results show that, for 4 K 15-field rule sets, our prototype on a state-of-the-art FPGA can achieve 250 Million Packets Per Second (MPPS) throughput. Using the proposed power optimization techniques, our classification engine consumes 30 % of the power without sacrificing the throughput.

关键词： packet classification field programmable gate arrays power budget Energy sources Engines throughput Power (Psychology)

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A Variable Length Hash Method for Faster Short Read Mapping on FPGA 25

A Variable Length Hash Method for Faster Short Read Mapping ...

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25th international conference on field programmable logic and applications

作者： Sogabe, Yoko Maruyama, Tsutomu Univ Tsukuba Syst & Informat Engn 1-1-1 Ten Nou Dai Tsukuba Ibaraki 3058573 Japan

ISBN: (纸本)9781467381239

Short read mapping is a process to align the short reads, which are fixed-length fragments of the target genome, to a given reference genome to identify the mutations in the target genome. Because of the rapid development of Next Generation Sequencing (NGS) technologies, faster short read mapping is required. In this paper, we propose a variable length hash method to further accelerate FPGA short read mapping systems. In the hash-based short read mapping algorithms, a fixed length sub-string of each short read, called seed, is used as the key. However, many different seeds are mapped into the same hash slots because of the high ununiformity of the human genome, and many fruitless key comparisons are performed. To equalize the slot size, we propose an optimized hash function that changes the bit masks adaptively. With this approach, it is possible to improve the performance of all FPGA short read mapping systems based on hash functions. the performance for the comparison in our FPGA system on a Xilinx XC7VX690T and XC6VLX240T can be improved two-times, and the total performance outperforms any existing FPGA systems.

关键词： field programmable gate arrays (FPGA)

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An LZ77-Style Bit-Level Compression for Trace Data Compaction 25

An LZ77-Style Bit-Level Compression for Trace Data Compactio...

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25th international conference on field programmable logic and applications

作者： Irrgang, Kai-Uwe Preusser, thomas B. Brandenburg Tech Univ Cottbus Senftenberg Inst Med Technol Cottbus Germany Tech Univ Dresden Inst Comp Engn Dresden Germany

ISBN: (纸本)9781467381239

Online tracing is a powerful technique for monitoring and debugging embedded processors. the amount of data produced by tracing is enormous. thus, an on-the-fly trace data reduction close by its source is extremely valuable. Trigger-driven filtering and a compressed trace representation are popular measures to take. While effective methods for the compression of branch target addresses in instruction traces are known, modern processors also produce extensive execution bit streams to log the execution of conditional instructions. this paper proposes an LZ77-style compressor for these bit streams. In contrast to classic implementations, it operates on the bit level. It is demonstrated that this compressor is effective even when using a small dictionary. this allows an implementation within an FPGA close by the source or even on the same chip as the trace source. It is also shown that the compressor can keep pace with practically relevant trace data sources.

关键词： Data compression Compressors Bit Level level compression Trace bit stream Legal Executions data reduction Data sources field programmable gate arrays PROCESSOR Binary digits instruction tracing compression

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Wotan: A Tool for Rapid Evaluation of FPGA Architecture Routability Without Benchmarks 25

Wotan: A Tool for Rapid Evaluation of FPGA Architecture Rout...

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25th international conference on field programmable logic and applications

作者： Petelin, Oleg Betz, Vaughn Univ Toronto Dept Elect & Comp Engn Toronto ON Canada

ISBN: (纸本)9781467381239

FPGA routing architectures consist of routing wires and programmable switches which together account for a significant portion of the fabric delay and area. Routing architectures have traditionally been evaluated using a full CAD flow with a suite of benchmark circuits. While the results of such a flow can be accurate, CAD tools are often tuned to a specific architecture type and can take a long time to run which prohibits quick exploration of different architectures early in the design process. In this paper we present an alternative approach that quickly estimates routability for a wide range of architectures without the use of benchmark circuits. Our new routability predictor first assigns congestion probabilities to the architecture's routing resources based on demand estimates found via efficient path enumeration through the routing graph. Next, we compute the probabilities of successfully routing different source/sink connections and finally we combine them to assign an overall routability score. We describe our predictor and present routability estimates for a range of 6-LUT and 4-LUT architectures, showing reasonable agreement with routability results from the full VPR CAD flow in much less CPU time.

关键词： ARCHITECTURE BENCHMARKS Network routing Building construction design process field programmable gate arrays Computer-Aided Design DFFB gene CPU time

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