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Hoplite: Building Austere Overlay NoCs for FPGAs 25

Hoplite: Building Austere Overlay NoCs for FPGAs

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25th international conference on field programmable logic and applications

作者： Kapre, Nachiket Gray, Jan Nanyang Technol Univ 50 Nanyang Ave Singapore Singapore Gray Res LLC Bellevue WA USA

ISBN: (纸本)9781467381239

Customized unidirectional, bufferless, deflectionrouted torus networks can outperform classic, bidirectional, buffered mesh networks for single-flit-oriented FPGA applications by as much as 1.5x (best achievable throughputs for a 10 x 10 system) or 2.5x (allocating same FPGA resources to both NoCs) for uniform random traffic. We present Hoplite, an efficient, lightweight, fast FPGA overlay NoC that is designed to be small and compact by (1) eliminating input buffers, and (2) reducing the cost of switch crossbar that have traditionally limited speeds and imposed heavy resource costs in conventional FPGA overlay NoCs. We implement bufferless deflection routing cheaply, requiring the generation of only output multiplexer controls and no backpressure handshakes. Additionally, we use directional channels that help reduce crossbar cost by restricting the number of inputs to the crossbar to three instead of four. When compared to buffered mesh switches, FPGA-based deflection routers are approximate to 3.5x smaller (HLS-generated switch) and 2.5x faster (clock period) for 32b payloads. In a separate experiment, we hand-crafted a prototype RTL version of our switch with RLOCS that requires only 60 LUTs and 100 FFs per router and runs at 2.9 ns.

关键词： field programmable gate arrays (FPGA)

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Limits of FPGA Acceleration of 3D Green's Function Computation for Geophysical applications 25

Limits of FPGA Acceleration of 3D Green's Function Computati...

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25th international conference on field programmable logic and applications

作者： Kapre, Nachiket Kumar, Jayakrishnan Selva Gupta, Parjanya Masuti, Sagar Barbot, Sylvain Nanyang Technol Univ Sch Comp Engn Singapore 639798 Singapore Nanyang Technol Univ Earth Observ Singapore Singapore 639798 Singapore

ISBN: (纸本)9781467381239

FPGA-based accelerators can outperform multi-core, GPU and Xeon Phi based platforms by at as much as 2.8x for 3D Green's Function processing in geophysics while delivering superior energy efficiency. FPGAs can efficiently implement a complex mixture of compute patterns that include data-parallelism, reductions, dataflow and streaming computations using spatial parallelism to deliver these speedups and power benefits. Since 3D Green's Function is highly-parallel but communication bound, we optimize the FPGA implementation by considering loop restructuring and tiling optimizations to minimize and regularize off-chip accesses. Furthermore, we configure the FPGA to implement the key compute intensive kernels at double-precision as well as single-precision to exploit the uncertainty in measurements of earthquake monitoring sensors. For 512x512x512 problem size, the Xilinx SX475T (Maxeler MAX3) outperforms the fastest architecture by 1.1-1.4x (double-precision), 2.2-2.8x (single-precision) with 1.2x better energy efficiency.

关键词： Green's function double precision field programmable gate arrays geophysics Energy efficiency single precision measurement uncertainty

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Automatic Support for Multi-Module Parallelism from Computational Patterns 25

Automatic Support for Multi-Module Parallelism from Computat...

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25th international conference on field programmable logic and applications

作者： George, Nithin Lee, HyoukJoong Novo, David Owaida, Muhsen Andrews, David Olukotun, Kunle Ienne, Paolo Ecole Polytech Fed Lausanne Sch Comp & Commun Sci CH-1015 Lausanne Switzerland Stanford Univ Pervas Parallelism Laboratory Stanford CA 94305 USA Univ Arkansas Dept Comp Sci & Comp Engn Fayetteville AR 72701 USA

ISBN: (纸本)9781467381239

field programmable Gate Arrays (FPGAs) can be customized into application-specific architectures to achieve high performance and energy-efficiency. Unfortunately, they are yet to gain significant adoption by application developers due to their low-level programming model. Moreover, to obtain good performance in an FPGA design, one often needs to correctly parallelize computation and balance the computational throughput with the available data access bandwidth. To address the programming model problem, recent efforts have focused on composing applications out of parallel computational patterns, such as map, reduce, zipWith and foreach, and leveraging the properties of these patterns to generate highly parallel hardware modules capable of high performance. In this work, we focus on the problem of further improving the performance and show that we can utilize the knowledge of how data is consumed and produced by these computational patterns in conjunction with the information of the system architecture to automatically parallelize computations across multiple hardware modules. To achieve this, we automatically infer synchronization needs arising due to parallelization and generate a complete system that can obtain high performance for a given application. We evaluate our approach using seven applications from different domains and show that our automatically generated designs achieve performance improvements ranging from 1.8 to 9.4 times.

关键词： HIGH-PERFORMANCE hardware module AUTOMATIC multi modules field programmable gate arrays application developer Building systems parallelization Synclitism parallelism

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A Resilient, Flash-Free Soft Error Mitigation Concept for the CBM-ToF Read-Out Chain via GBT-SCA 25

A Resilient, Flash-Free Soft Error Mitigation Concept for th...

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25th international conference on field programmable logic and applications

作者： Oancea, Andrei-Dumitru Stuellein, Christian Gebelein, Jano Kebschull, Udo Goethe Univ Frankfurt Infrastruct & Comp Syst Data Proc Frankfurt Germany

ISBN: (纸本)9781467381239

the ToF detector read-out chain of the upcoming CBM experiment at FAIR will be equipped with FPGA-based read-out boards (ROBs), which are going to be operated in a radiation environment. Flash-based FPGAs are not an option for this experiment due to their low total ionizing dose limit compared to SRAM-based FPGAs, and therefore the latter is foreseen for the ROBs. Consequently, precautions against soft errors in the configuration memories of the FPGAs need to be taken to keep the chain operational. the proposed approach merges on-chip single upset correction with external intervention for multiple-bit upsets and resets. the external intervention is going to be implemented via the control path of the chain through the GBT-SCA, which offers a JTAG interface, as well as interrupt-capable GPIOs among other features. thus, the use of the GBT-SCA enables an event-driven configuration upset mitigation concept, while being itself radiation hardened by design. Conventional blind configuration scrubbing would cause a continuous load on the control path, while the selective frame scrubbing reduces this load significantly. the concept has been validated in beamtests conducted at COSY, FZ Juelich, Germany. the concept, the beamtest results and limitations of the implementation are presented and discussed in this paper.

关键词： trajectory control Upset sustained loads linearly ordered set washes field programmable gate arrays

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Serial and Parallel Interleaved Modular Multipliers on FPGA Platform 25

Serial and Parallel Interleaved Modular Multipliers on FPGA ...

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25th international conference on field programmable logic and applications

作者： Javeed, Khalid Wang, Xiaojun Scott, Mike Dublin City Univ Sch Elect Engn Dublin Ireland CertiVox UK London England

ISBN: (纸本)9781467381239

Modular multiplication is a core operation in all public key based cryptosystems. the performance of these cryptosystems can be enhanced substantially by incorporating an optimized modular multiplier. this paper presents serial and parallel radix-4 modular multipliers based on interleaved multiplication algorithm and Montgomery power laddering technique. A serial radix-4 interleaved modular multiplier provides 5 0 % reduction in the required clock cycles. In addition to the reduction in clock cycles, a parallel modular multiplier maintains a critical path delay comparable to the bit serial interleaved multipliers. the proposed designs are implemented in Verilog HDL and synthesized targeting virtex-6 FPGA platform using Xilinx ISE 14.2 Design suite. the serial radix-4 multiplier computes a 256-bit modular multiplication in 1.3 mu s, occupies 3.9K LUTs, and runs at 96 MHz. the parallel radix-4 multiplier takes 0.77 mu s, occupies 5.3K LUTs, and runs at 166 MHz. the results show that the parallel radix-4 modular multiplier provides 62 % and 49 % speed-up over the corresponding bit serial and bit parallel versions, respectively. thus, these designs are suitable to accelerate modular multiplication in many cryptographic processors.

关键词： Finite field elliptic curve cryptography (ECC) interleaved multiplication public key cryptography (PKC)

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Scavenger: Automating the Construction of Application-Optimized Memory Hierarchies 25

Scavenger: Automating the Construction of Application-Optimi...

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25th international conference on field programmable logic and applications

作者： Yang, Hsin-Jung Fleming, Kermin Adler, Michael Winterstein, Felix Emer, Joel MIT CSAIL Cambridge MA 02139 USA Intel Corp SSG Santa Clara CA 95051 USA European Space Agcy Ground Stn Syst Div F-75738 Paris 15 France NVIDIA Res Santa Clara CA USA

ISBN: (纸本)9781467381239

High-level abstractions separate algorithm design from platform implementation, allowing programmers to focus on algorithms while building increasingly complex systems. this separation also provides system programmers and compilers an opportunity to optimize platform services for each application. In FPGAs, this platform-level malleability extends to the memory system: unlike general-purpose processors, in which memory hardware is fixed at design time, the capacity, associativity, and topology of FPGA memory systems may all be tuned to improve application performance. Since application kernels often use few memory resources, substantial memory capacity may be available to the platform for use on behalf of the user program. In this work, we perform an initial exploration of methods for automating the construction of these application-specific memory hierarchies. Although exploiting spare resources can be beneficial, naively consuming all memory resources may cause frequency degradation. To relieve timing pressure in large BRAM structures, we provide microarchitectural techniques to trade memory latency for design frequency. We demonstrate, by examining both hand-assembled and HLS-compiled benchmarks, that our application-optimized memory system can improve preexisting application runtime by 25% on average.

关键词： field programmable gate arrays (FPGA)

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the Bel array: An asynchronous fine-grained co-processor for DSP

The Bel array: An asynchronous fine-grained co-processor for...

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international conference on Signal Processing and Communication Systems, ICSPCS

作者： Andrew Przybylski Kashfia Haque Paul Beckett School of Engineering RMIT University Melbourne Australia

ISBN: (纸本)9781509009428

this paper analyses the Bit-Element (Bel) Array, a fine-grained (single-bit) asynchronous reconfigurable 2D array designed using NULL Convention logic (NCL) set up as a coprocessor for Digital Signal Processing (DSP) applications. Each Bel can perform a limited number of two-input Boolean gate functions, inversion, routing or produce 1-bit constant values. this fine grained reconfigurable fabric exhibits spatial computing characteristics that can provide massive parallelism within and across micro-pipelines. NCL implementation enables operation over a broad voltage range to suit (slower) low power operation, or low latency and high performance (higher power). An example DSP application, a single-bit Delta Sigma 20-tap Short Word Length (SWL) Finite Impulse Response (FIR) filter is used to illustrate the mapping and configuration process, occupying an effective area less than 0.164 square millimeters on a 28 nm process.

关键词： logic gates field programmable gate arrays Digital signal processing logic arrays Hardware Arrays

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Software-in-the-Loop Simulation of Embedded Control applications based on Virtual Platforms Software-in-the-Loop with Open Virtual Platforms (OVP) using real world data and devices 25

Software-in-the-Loop Simulation of Embedded Control Applicat...

引用

25th international conference on field programmable logic and applications

作者： Werner, Stephan Masing, Leonard Lesniak, Fabian Becker, Juergen Karlsruhe Inst Technol Inst Informat Proc Technol ITIV Karlsruhe Germany

ISBN: (纸本)9781467381239

One challenge in developing complex software for embedded systems is the missing option of rapid prototyping in early stages of the development cycle. In this paper we present the use of the High Level Simulation Framework "Open Virtual Platforms" (OVP) for Software-in-the-Loop simulation of embedded control applications. therefore, we investigate and evaluate different methods allowing the data exchange between the simulated platform and the host machine running the simulation environment. the insights we gain are used to design peripherals which appear to the simulated processor system like devices available on the targeted hardware platform and allow the access to files stored on the host machine on one hand, and the communication with hardware devices connected to the host on the other hand. In both cases the cross-compiled application code for the targeted embedded platform including the operating system (OS) and the hardware abstraction layer (HAL) can be executed by the virtual platform (VP) without any modifications. Additionally, we introduce a method for controlling the synchronization of OVP with the host, which can be used to either run simulations in fast motion mode, or to collaborate with hardware devices or other applications. the approach is verified with two use cases: (1) a motor control application processing data by accessing files and (2) an image processing application interacting with real hardware devices directly coupled with the virtual platform.

关键词： Virtual Platforms Software-in-the-Loop OVP Virtual Prototyping embedded control applications Cyber Physical Systems

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High-Level-Synthesis Extensions for Scalable Single-Chip Many-Accelerators on FPGAs 25

High-Level-Synthesis Extensions for Scalable Single-Chip Man...

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25th international conference on field programmable logic and applications

作者： Diamantopoulos, Dionysios Xydis, Sotirios Siozios, Kostas Soudris, Dimitrios Natl Tech Univ Athens Sch Elect & Comp Engn GR-10682 Athens Greece

ISBN: (纸本)9781467381239

Accelerator-coupled systems have been introduced as a promising architectural paradigm that can boost performance and improve power of general-purpose computing platforms. this research focuses on the accelerators' scalability problem due to resource under-utilization in FPGA-based accelerator-coupled platforms. By recognizing that static memory allocation the de-facto memory management mechanism supported by modern design techniques and synthesis tools forms the main source of memory-induced under-utilization, i.e. leading up to 75% of dark silicon, we propose the development of a) a Single-Chip Many-Accelerator (SCMA) architecture that reduces energy budget by providing high-throughput processing nodes hooked under the same low-latency FPGA die and b) a novel design framework that extends conventional RTL and High Level Synthesis (HLS) design flows with dynamic memory management (DMM) features to leverage scalability by enabling accelerators to dynamically adapt their allocated memory to the runtime memory requirements, thus maximizing the overall accelerator count through effective sharing of FPGA's memories resources. By applying these novel techniques in the state-of-art Vivadof-HoLS tool, we managed to increase accelerator density up to 3.8x that trade-off per-accelerator latency overhead (1.2 x - 19.9 x) with overall system's throughput (2.6 x - 23.1 x) and performance-perwatt (0.09 x - 21.7 x).

关键词： Scalability field programmable gate arrays Energy budget Accelerators allocate memory static memory Memory Platform high level synthesis

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FPGA Implementation to Estimate the Number of Endmembers in Hyperspectral Images 25

FPGA Implementation to Estimate the Number of Endmembers in ...

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25th international conference on field programmable logic and applications

作者： Gonzalez, Carlos Mozos, Daniel Lopez, Sebastian Sarmiento, Roberto Univ Complutense Madrid Dept Comp Architecture & Automat C Prof Jose Garcia Santesmases 9 Madrid 28040 Spain Univ Las Palmas Gran Canaria Inst Appl Microelect IUMA Las Palmas Gran Canaria 35017 Spain

ISBN: (纸本)9781467381239

Spectral unmixing is an important task for remotely sensed hyperspectral data exploitation. It amounts the identification of pure spectral signatures (endmembers) in the data, and the estimation of the abundance of each endmember in each (possibly mixed) pixel. A challenging problem in spectral unmixing is how to determine the number of endmembers in a given scene. For this purpose, many algorithms have been proposed in the recent literature, being the estimation of the Virtual Dimensionality (VD) of the hyperspectral image and the hyperspectral signal subspace estimator (HySime) two of the most popular choices. Unfortunately, the high dimensionality of the hyperspectral data provided by modern sensors as well as the inherent computational complexity clearly make the use of these algorithms prohibitive for applications under real-time or near real-time constraints. Hence, the utilization of high performance computing platforms in order to accelerate the process of unmixing a hyperspectral image becomes mandatory for such scenarios. Reconfigurable hardware solutions such as field programmable gate arrays (FPGAs) have consolidated during the last years as one of the preferred choices for the fast processing of hyperspectral remotely sensed images due to their advantages over other high performance computing systems, such as clusters of computers, multicore processors and/or graphical processing units (GPUs). this paper uncovers two FPGA-based architectures for accelerating the process of estimating the number of endmembers that constitute a hyperspectral image according to the VD and the HySime algorithms. the proposed methods have been implemented on a Virtex-7 XC7VX690T FPGA and tested using real hyperspectral data collected by NASAs Airborne Visible Infra-Red Imaging Spectrometer (AVIRIS) over the Cuprite mining district in Nevada and the World Trade Center in New York. Experimental results demonstrate that the VD implementation exhibits real-time performance while

关键词： hyperspectral imagery field programmable gate arrays Sexually Transmitted Diseases High Performance Computing software release exsolution quasi-realtime language

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