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Novel lightweight FF-APUF design for FPGA

Novel lightweight FF-APUF design for FPGA

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IEEE international SOC conference

作者： Chongyan Gu Yijun Cui Neil Hanley Máire O'Neill CSIT Queen's University Belfast Belfast U.K. Nanjing University of Aeronautics and Astronautics Nanjing China

ISBN: (纸本)9781509013685

Physical unclonable functions (PUFs), are a new type of physical security primitive which enable digital identifiers to be extracted from devices, such as field programmable gate arrays (FPGAs) or application specific integrated circuits (ASICs). Due to their flexibility and lower time to market, FPGAs are increasingly used for many applications. Arbiter PUFs (APUFs) are among the most widely studied PUF designs. However, they often suffer from poor uniqueness and reliability characteristics, are difficult to implement in FPGAs and consume excessive FPGA resources. To address these problems, a new Flip-flop based APUF (FF-APUF) design is proposed that offers a compact architecture, combined with strong uniqueness and good reliability. It is specifically designed for FPGAs. the proposed work is verified on a low-cost Nexys4 board based on the latest 28 nm technology Xilinx Artix-7 FPGA. the proposed FF-APUF circuit for generating a 1-bit response consumes only 44 slices, which is a saving of more than 66% in hardware resources over previous related research. Moreover, experimental results show improvements in both uniqueness and reliability. In particular, the expected uniqueness of the response bits is 40% on FPGA, which significantly improves upon a uniqueness of 9% achieved in previous work.

关键词： Reliability logic gates field programmable gate arrays Latches

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Reconfigurable analog classifier for knee-joint rehabilitation

Reconfigurable analog classifier for knee-joint rehabilitati...

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Annual international conference of the IEEE Engineering in Medicine and Biology Society (EMBC)

作者： Sahil Shah Hakan Toreyin Omer T. Inan Jennifer Hasler School of Electrical and Computer Engineering Georgia Institute of Technology Atlanta Georgia

ISBN: (纸本)9781457702198

We present a System-On-Chip field programmable Analog Array (FPAA) for analyzing and processing the signals off an accelerometer for a wearable joint health assessment device. FPAAs have been shown to compute with an efficiency of 1000 times, as well as area efficiencies of 100 times, more than digital solutions. this work presents a low power signal processing system which allows us to extract features from the output of the accelerometer. these features are used by the classifier, implemented using a vector matrix multiplication and a two output 1-winner-take-all, to detect flexion and extension cycles in the subject. the compiled design consumes 0.636 μW of power for the front end analog signal processing chain where as the single layer classifier uses 13 μW of power. thus the system is highly suitable for wearable applications where power consumption is a major concern. the current FPAA is fabricated in a 0.35 μm CMOS process and is operated at a power supply of 2.5 volts. the Gm-C filters and other circuits are operated in the subthreshold regime of the transistor to obtain the highest transconductance to current ratio offered by the process.

关键词： field programmable analog arrays Accelerometers Virtual machine monitors Feature extraction Band-pass filters logic gates

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A Flexible Profiling Sub-System for Reconfigurable logic Architectures

A Flexible Profiling Sub-System for Reconfigurable Logic Arc...

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Euromicro conference on Parallel, Distributed and Network-Based Processing

作者： G. Valente V. Muttillo L. Pomante F. Federici M. Faccio A. Moro S. Ferri C. Tieri DEWS Center of Excellence Università Degli Studi Dell'Aquila L'Aquila Italy

In recent years, embedded applications have been characterized by increasingly stringent requirements, both from functional and non-functional point of view. this led to the adoption of complex hardware platforms (multi-core and many-core architectures), able to guarantee high computational power with low energy consumption and reduced footprint. An efficient characterization of these platforms can be problematic, given the large number of hardware resources and the complexity of software applications. For this reason, the need for a runtime analysis support should be taken in account during the design phase (a design "for monitorability"). this paper introduces "Adaptive Profiling Hardware Sub-system" (AIPHS), a hardware profiling tool supporting the development of runtime monitorable systems. Two different multicore platforms are considered in order to evaluate AIPHS functionalities: an asymmetric dual-MicroBlaze system and a quad-Leon3 system supporting symmetric multiprocessing.

关键词： FPGAs Leon3 MicroBlaze Multi-core architectures OpenMP Profiling core construction symmetric multiprocessor Reconfigurable logic field programmable gate arrays ARCHITECTURE hardware resource applications software low energy consumption computational power Platform design phases Runtime

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Exploring static and dynamic flash-based FPGA design topologies

Exploring static and dynamic flash-based FPGA design topolog...

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IEEE international conference on Computer Design: VLSI in Computers and Processors, (ICCD)

作者： Monther Abusultan Sunil P Khatri ECE Department Texas A&M University College Station TX

field programmable gate arrays (FPGAs) are the implementation platform of choice when it comes to design flexibility. However, SRAM-based FPGAs suffer from high power consumption, prolonged boot delays (due to the volatility of the configuration bits), and a significant area overhead (due to the use of 5T SRAM cells for the configuration bits). Floating gate (flash) based FPGAs can avert these problems. this paper presents a study of flash-based FPGA designs (both static and dynamic), and presents the tradeoff of delay, power dissipation and energy consumption of the various designs. Our work differs from previously proposed flash-based FPGAs, since we embed the flash transistors (which store the configuration bits) directly within the logic and interconnect fabrics. We also present a detailed description of how the programming of the configuration bits is accomplished. Our delay and power estimates are derived from circuit level simulations. Our proposed static flash-based LUT structure yields 10% faster operation, 12% lower dynamic power dissipation, 21% lower energy consumption and 29% lower static power dissipation compared to a traditional SRAM-based LUT. We also show that, for high performance applications, a dynamic flash-based LUT can achieve further performance improvements (32% lower delay) with higher energy consumption (37% higher) compared to an SRAM-based LUT. We also show that a flash-based interconnect structure provides 89% lower delay and 71% lower overall power consumption compared to the traditional interconnect structure used in SRAM-based FPGAs.

关键词： field programmable gate arrays Table lookup logic gates Transistors Delays Nonvolatile memory Integrated circuit interconnections

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Binarization-based Human Detection with Hardware Reconfigurability 17

Binarization-based Human Detection with Hardware Reconfigura...

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2015 IEEE 17th international conference on High Performance Computing and Communications (HPCC)

作者： Li, Yibin Jia, Zhiping Xie, Shuai Shandong Univ Comp Sci & Engn Sch Jinan Peoples R China

ISBN: (纸本)9781479989379

Limitations in power and resources make the implementation of human detection a challenging issue for embedded applications, such as wireless multimedia sensor networks (WMSNs). To address this issue, binarization-based optimization is presented in this study. By implementing this optimization, the required calculations and memory space for the hardware realization of human detection can be minimized. Meanwhile, the human detection system is deployed in a variety of environments. as there is the large variation among different environments, a custom classifier, which is trained on a data-sets similar to the deployed environment, can deliver the better accuracy compared to the generic classifier. therefore, the partial dynamic reconfiguration of a field programmable gate array (FPGA) is utilized to enable multiple classifiers in this paper. the classifier can be updated remotely for embedded implementation. Initial experimental results demonstrate that the proposed implementation achieved 348 fps by using a Xilinx Virtex-5 FPGA. the detection accuracy achieved a miss rate of 1.97% and a false positive rate of 1%. Compared to the state-of-art, the power consumption can reduce up to 36%. In this paper, remote hardware reconfigurablity is enabled. the newly trained classifier can be updated through wireless communication. To our knowledge, it is the first work to implement the Scene-adaptive classifier in hardware and combine it with remotely DPR function of FPGA.

关键词： field programmable gate arrays Object detection Wireless sensor networks

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A Parallelizing Matlab Compiler Framework and Run time for Heterogeneous Systems 17

A Parallelizing Matlab Compiler Framework and Run time for H...

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2015 IEEE 17th international conference on High Performance Computing and Communications (HPCC)

作者： Skalicky, Sam Lopez, Sonia Lukowiak, Marcin Schmidt, Andrew G. Rochester Inst Technol Dept Comp Engn Rochester NY 14623 USA Univ Southern Calif Inst Informat Sci Los Angeles CA 90089 USA

ISBN: (纸本)9781479989379

Compute-intensive applications incorporate ever increasing data processing requirements on hardware systems. Many of these applications have only recently become feasible thanks to the increasing computing power of modern processors. the Matlab language is uniquely situated to support the description of these compute-intensive scientific applications, and consequently has been continuously improved to provide increasing computational support in the form of multithreading for CPUs and utilizing accelerators such as GPUs and FPGAs. Moreover, to take advantage of the computational support in these heterogeneous systems from the problem domain to the computer architecture necessitates a wide breadth of knowledge and understanding. In this work, we present a framework for the development of compute-intensive scientific applications in Matlab using heterogeneous processor systems. We investigate systems containing CPUs, GPUs, and FPGAs. We leverage the capabilities of Matlab and supplement them by automating the mapping, scheduling, and parallel code generation. Our experimental results on a set of benchmarks achieved from 20x to 60x speedups compared to the standard Matlab CPU environment with minimal effort required on the part of the user.

关键词： graphics processing units mathematics computing multi-threading parallel architectures parallelising compilers FPGA GPU Matlab compiler framework Matlab language compute-intensive scientific application computer architecture heterogeneous processor system heterogeneous system multithreading parallel code generation standard Matlab CPU environment Data transfer field programmable gate arrays Kernel MATLAB Message systems Processor scheduling Scheduling Heterogeneous computing Matlab compiler MATLAB Multithreading field programmable gate arrays HETEROGENEOUS SYSTEM Computer Architecture Computer based information systems mathematics computing compilers scheduling of multiprocessor Code generation data transmission Parallel architectures Graphics Processing Unit central processing units

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Hypergraph-Cover Diversity for Maximally-Resilient Reconfigurable Systems 17

Hypergraph-Cover Diversity for Maximally-Resilient Reconfigu...

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2015 IEEE 17th international conference on High Performance Computing and Communications (HPCC)

作者： Alzahrani, Ahmad DeMara, Ronald F. Univ Cent Florida Dept Elect Engn & Comp Sci Orlando FL 32816 USA

ISBN: (纸本)9781479989379

Scaling trends of reconfigurable hardware (RH) and their design flexibility have proliferated their use in dependability-critical embedded applications. Although their reconfigurability can enable significant fault tolerance, due to the complexity of execution time in their design flow, in-field reconfigurability can be infeasible and thus limit such potential. this need is addressed by developing a graph and set theoretic approach, named hypergraph-cover diversity (HCD), as a preemptive design technique to shift the dominant costs of resiliency to design-time. In particular, union-free hypergraphs are exploited to partition the reconfigurable resources pool into highly separable subsets of resources, each of which can be utilized by the same synthesized application netlist. the diverse implementations provide reconfiguration-based resilience throughout the system lifetime while avoiding the significant overheads associated with runtime placement and routing phases. Two novel scalable algorithms to construct union-free hypergraphs are proposed and described. Evaluation on a Motion-JPEG image compression core using a Xilinx 7-series-based FPGA hardware platform demonstrates a statistically significant increase in fault tolerance and area efficiency when using proposed work compared to commonly-used modular redundancy approaches.

关键词： data compression embedded systems field programmable gate arrays graph theory image coding motion estimation reconfigurable architectures HCD Motion-JPEG image compression core RH Xilinx 7-series-based FPGA hardware platform area efficiency dependability-critical embedded applications design flexibility execution time fault tolerance hypergraph-cover diversity in-field reconfigurability maximally-resilient reconfigurable systems preemptive design technique reconfigurable hardware reconfigurable resource partitioning reconfiguration-based resilience resiliency costs routing phases runtime placement separable resource subsets set theoretic approach statistical analysis synthesized application netlist union-free hypergraphs Circuit faults Embedded systems Fault tolerance Fault tolerant systems field programmable gate arrays Hardware Runtime Area Efficiency Design Diversity FPGAs

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Performance analysis of transistor-based circuits through TAMAMS Web: From bulk to molecular devices

Performance analysis of transistor-based circuits through TA...

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international conference on Electronic Devices, Systems and applications (ICEDSA)

作者： Izhar Hussain Fabrizio Riente Massimo Ruo Roch Gianluca Piccinini Mariagrazia Graziano Department of Electronics and Telecommunications Politecnico di Torino Italy

ISBN: (纸本)9781509053070

To meet the challenges associated with transistor scaling and short channel devices, the structure of MOS devices has undergone an incredible evolution. From Bulk devices, technology has shifted through Silicon-On-Insulator (SOI) devices, reaching now FinFET transistors, the next steps in the evolutionary path are represented by Gate-All-Around (GAA) and Molecular Transistors. Using analytical compact models for standard (BULK, SOI, FinFET) and emerging devices (GAA, Molecular FET (MOLFET)), it is possible to predict the system level performance of future NANO electronic circuits. In this work, we show how circuit's performance can be predicted and analyzed at system level using our tool, TAMTAMS Web. Starting from Bulk transistors down to a nanometer scale Molecular FET, TAMTAMS Web incorporates models to analyze device quantities (Drive current, Subthresold current...) up to system level. We have developed a compact model of Virtex 4 FPGA CLB block that is used as benchmark. the work here presented not only highlights the potentialities of TAMTAMS, but it also provides useful hints on the evolution of transistor based technology.

关键词： Transistors logic gates field programmable gate arrays Gallium arsenide Semiconductor device modeling Integrated circuit modeling Performance evaluation

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Review of NoC-Based FPGAs Architectures 5

Review of NoC-Based FPGAs Architectures

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5th international conference on Energy Aware Computing Systems & applications (ICEAC)

作者： Salaheldin, Alaa Abdallah, Karim Gamal, Noha Mostafa, Hassan Cairo Univ Elect & Commun Engn Dept Giza 12613 Egypt AUC Ctr Nanoelect & Devices New Cairo 11835 Egypt Zewail City Sci & Technol New Cairo 11835 Egypt

ISBN: (纸本)9781479917723

Nowadays, FPGAs serve as fields programmable Systems on Chip (FPSoC) and are widely used to implement computationally intensive world applications. As the number of components in FPSoCs increases, the interconnect schemes based on Network on Chip (NoC) approach are increasingly used to overcome the problems of traditional bus based and point-to-point interconnect scheme. In this paper, we review several designs based on their contributions, architectures, implementations and future works. We also made our comparison between three of these routes to analyze the effect of varying the number of Virtual Channels (VCs), flit data width and buffer depth on the operating frequency, logic Look-Up Tables (LUTs) and registers to help choosing the appropriate NoC based on system requirements.

关键词： field programmable gate arrays Network topology Ports (Computers) Registers Routing Table lookup field programmable gate arrays Table lookup Registers Network topology Network routing ARCHITECTURE system requirements

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CoRAM++: Supporting data-structure-specific memory interfaces for FPGA computing 25

CoRAM++: Supporting data-structure-specific memory interface...

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25th international conference on field programmable logic and applications, FPL 2015

作者： Weisz, Gabriel Hoe, James C. Carnegie Mellon University PittsburghPA United States

ISBN: (纸本)9780993428005

Facilitating DRAM access is an essential part of an application programming environment for FPGA computing. Existing FPGA application programming environments primarily focus on support for simple, regular memory access patterns, such as block copy and streaming. this paper presents CoRAM++, a programming environment for FPGA computing that is based on an extensible set of data-structure-specific memory interfaces. CoRAM++ supports complex data structures, such as multidimensional arrays and linked lists, in addition to simple data access patterns. CoRAM++ defines an appropriate application-level interface for each supported data structure, and provides a specialized soft-logic implementation of the supporting datapath to memory We evaluated the effectiveness of the CoRAM++ data-structure-specific approach in three application scenarios based on streams, multi-dimensional arrays and linked lists. Our results show that the CoRAM++ programming environment can offer convenient application-level interfaces without penalizing DRAM access performance. © 2015 Imperial College.

关键词： field programmable gate arrays (FPGA)

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