检索结果-内蒙古大学图书馆

17th international conference on field programmable logic and applications

作者： Voigt, Sven-Ole Teufel, thomas Hamburg Univ Technol Inst Reliable Comp D-21073 Hamburg Germany

ISBN: (纸本)9781424410590

In this paper we present an FPGA-based dataflow architecture that both efficiently computes parallel algorithms using dedicated FPGA resources and scales well to multi-FPGA chip designs while the overall communication bandwidth increases. the basic idea is based on reconfiguration. In contrast to the concept of partially reconfiguring FPGAs, our approach is to connect computational units via a dynamically variable topology. the latter consists of dedicated switches which are individually controlled by simple shift registers. Hence, the computational result is a function of the currently configured interconnection pattern that can be updated within one single clock cycle. the scalability of this architecture is shown on a high-performance parallel FFT.

关键词： field programmable gate arrays (FPGA)

来源：评论

学校读者我要写书评

暂无评论

Discrete event simulation of molecular dynamics with configurable logic

Discrete event simulation of molecular dynamics with configu...

引用

17th international conference on field programmable logic and applications

作者： Model, Josh Herbordt, Martin C. Boston Univ Dept Elect & Comp Engn Boston MA 02215 USA

ISBN: (纸本)9781424410590

Molecular dynamics simulation based on discrete event simulation (DMD) is emerging as an alternative to time-step driven molecular dynamics (MD). DMD uses simplified discretized models, enabling simulations to be advanced by event, with a resulting performance increase of several orders of magnitude. Even so, DMD is compute bound. Moreover, unlike MD, causality issues make DMD difficult to scale, with O(root p) being the best so far achieved. We find that FPGAs are extremely well suited to accelerating DMD. the chaotic execution, which results in there being virtually no prediction window, is overcome with a long processing pipeline augmented with associative structures analogous to those used in CPU reorder buffers. Our primary result is a microarchitecture for DMD that processes events with a throughput equal to a small multiple of the FPGA's clock, resulting in a hundred-fold speed-up over serial implementations.

关键词： Dynamic mode decomposition

来源：评论

学校读者我要写书评

暂无评论

L4: An FPGA-based accelerator for detailed maze routing

L4: An FPGA-based accelerator for detailed maze routing

引用

17th international conference on field programmable logic and applications

作者： Nestor, John A. Lavine, JeremY Lafayette Coll ECE Dept Easton PA 18042 USA

ISBN: (纸本)9781424410590

this paper describes an FPGA-based accelerator for maze routing applications such as integrated circuit detailed routing. the accelerator efficiently supports multiple layers, multi-terminal nets, and rip up and reroute. By time-multiplexing multiple layers over a two-dimensional array of processing elements, this approach can support multi-layer grids large enough for detailed routing while providing at 1-2 orders of magnitude speedup over software running on a modern desktop computer. the current implementation supports a 32 X 32 routing grid with up to 16 layers in a single Xilinx XC2V6000 FPGA. Up to 64 X 64 routing grids are feasible in larger commercially available FPGAs. Performance measurements (including interface overhead) show a speedup of 29X-93X over the classic Lee Algorithm and 5X-19X over the A* Algorithm. An improved interface design could yield significantly larger speedups.

关键词： field programmable gate arrays (FPGA)

来源：评论

学校读者我要写书评

暂无评论

Adaptive thermoregulation for applications on reconfigurable devices

Adaptive thermoregulation for applications on reconfigurable...

引用

17th international conference on field programmable logic and applications

作者： Jones, Phillip H. Moscola, James Cho, Young H. Lockwood, John W. Washington Univ Appl Res Lab St Louis MO 63130 USA

ISBN: (纸本)9781424410590

A biological organism's ability to sense and adapt to its environment is essential to its survival. Likewise, environmentally aware computing systems avail themselves to a longer operational life and a wider range of applications than traditional systems. In this paper, we propose a novel circuit design methodology that allows parameterizable hardware to self-regulate its temperature. We apply this methodology to an image recognition system on an Xilinx Virtex 4 FX100 field programmable gate array (FPGA). the image recognition system sustains a safe operational temperature by automatically adjusting its frequency and output quality. the circuit sacrifices output performance and quality to lower its internal temperature as the ambient temperature increases, and can leverage cooler temperatures by increasing output performance and quality. Furthermore, the circuit will shutdown if the ambient temperature becomes too hot for the device to function properly. A performance evaluation of our adaptive circuit under various thermal conditions shows up to a 4x factor increase in performance and a 2x factor increase in quality over a system without dynamic thermal control.

关键词： field programmable gate arrays (FPGA)

来源：评论

学校读者我要写书评

暂无评论

FPGA implementation of a data-driven stochastic biochemical simulator with the next reaction method

FPGA implementation of a data-driven stochastic biochemical ...

引用

17th international conference on field programmable logic and applications

作者： Yoshimi, Masato Iwaoka, Yow Nishikawa, Yuri Kojima, Toshinori Osana, Yastmori Funahashi, Akira Hiroi, Noriko Shibata, Yuichiro Iwanaga, Naoki Kitano, Hiroaki Amano, Hideharu Keio Univ Yokohama Kanagawa 223 Japan JST ERATO SORST Kitano Symbiot Syst Project Tokyo Japan Nagasaki Univ Nagasaki Japan

ISBN: (纸本)9781424410590

this paper introduces a scalable FPGA implementation of a stochastic simulation algorithm (SSA) called the Next Reaction Method. there are some hardware approaches of SSAs that obtained high-throughput on reconfigurable devices such as FPGAs, but these works lacked in scalability. the design of this work can accommodate to the increasing size of target biochemical models, or to make use of increasing capacity of FPGAs. Interconnection network between arithmetic circuits and multiple simulation circuits aims to per-form a data-driven multi-threading simulation. Approximately 8 times speedup was obtained compared to an execution on Xeon 2.80GHz.

关键词： field programmable gate arrays (FPGA)

来源：评论

学校读者我要写书评

暂无评论

High level abstraction language as an alternative to embedded processors for internet packet processing in FPGA

High level abstraction language as an alternative to embedde...

引用

17th international conference on field programmable logic and applications

作者： Dedek, Tomas Martinek, Tomas Marek, Tomas CESNET Zspo Zikova 4 Prague 16000 6 Czech Republic ASICentrum sro Prague 14221 Czech Republic

ISBN: (纸本)9781424410590

In this paper, we investigate three different realizations of the same block from different points of view. the mentioned different realizations include two realizations with embedded processors (custom 16-bit RISC processor and general soft-core processor) and the third realization uses Handel-C as an example of synthesisable high-level abstraction languages. the results show that development time of complete solution (HW and SW) is approximately the same for the Handel-C design and the design with soft-core processor;the development time of the Custom 16-bit RISC processor is about five times higher. Moreover, the throughput of the Handel-C design measured in the number of bits processed in one second is the highest. the obtained frequency and occupied area of the Handel-C design depends on the complexity of the used program. However, results are comparable or even better than results of the embedded processors.

关键词： field programmable gate arrays (FPGA)

来源：评论

学校读者我要写书评

暂无评论

Multi-processor system-level synthesis for multiple applications on platform FPGA

Multi-processor system-level synthesis for multiple applicat...

引用

17th international conference on field programmable logic and applications

作者： Kumar, Akash Fernando, Shakith Ha, Yajun Mesman, Bart Corporaal, Henk Eindhoven Univ Technol POB 513 NL-5600 MB Eindhoven Netherlands Natl Univ Singapore ECE Dept Singapore Singapore

ISBN: (纸本)9781424410590

Multiprocessor systems-on-chip (MPSoC) are being developed in increasing numbers to support the high number of applications running on modern embedded systems. Designing and programming such systems prove to be a major challenge. Most of the current design methodologies rely on creating the design by hand, and are therefore error-prone and time-consuming. this also limits the number of design points that can be explored. While some efforts have been made to automate the flow and raise the abstraction level, these are still limited to single-application designs. In this paper, we present a design methodology to generate and program MPSoC designs in a systematic and automated way for multiple applications. the architecture is automatically inferred from the application specifications, and customized for it. the flow is ideal for fast design space exploration (DSE) in MPSoC systems. We present results of a case study to compute the buffer-throughput trade-offs in real-life applications, H263 and JPEG decoders. the generation of the entire project takes about 100ms, and the whole DSE was completed in 45 minutes, including the FPGA mapping and synthesis.

关键词： field programmable gate arrays (FPGA)

来源：评论

学校读者我要写书评

暂无评论

A hardware algorithm for the minimum p-quasi clique cover problem

A hardware algorithm for the minimum <i>p</i>-quasi clique c...

引用

17th international conference on field programmable logic and applications

作者： Watanabe, Shuichi Kitamichi, Junji Kuroda, Kenichi Kawasaki Microelect Inc Mihama Ku Makuhari Techno Garden B-11F 1-3 Nakase Chiba 2618501 Japan Univ Aizu Sch Comp Sci & Engn Fukushima 9658580 Japan

ISBN: (纸本)9781424410590

In this paper, we describe a hardware algorithm for the minimum p-quasi clique cover (MPQCC) problem and its implementation on an FPGA. MPQCC problem is a combinational optimization problem that is NP-complete. Furthermore, gene expression profile analysis is one of applied fields of MPQCC problem. We aim to develop an inexpensive acceleration system using FPGAs for gene expression profile analysis. We adopt a Hopfield neural network for the proposed algorithm for the reduction of the calculation time. the proposed architecture using a ring network can execute the proposed algorithm effectively on FPGAs because each module can run in parallel independently and the system can be implemented with simple placement and routing of modules, and high scalability. We show that the proposed method is better than the existing one with regard to its solution searching ability and required calculation time.

关键词： field programmable gate arrays (FPGA)

来源：评论

学校读者我要写书评

暂无评论

FPGA programmable logic block evaluation using quantified Boolean satisfiability

引用

IEE PROCEEDINGS-COMPUTERS AND DIGITAL TECHNIQUES 2006年第3期153卷 165-172页

作者： Ling, A. C. Singh, D. P. Brown, S. D. Univ Toronto Toronto ON M5S 3G4 Canada Altera Toronto Technol Ctr Toronto ON M5S 1S4 Canada

A novel field programmable gate array (FPGA) logic synthesis technique that determines if a logic function can be implemented in a given programmable circuit is presented, and how this problem can be formalised and solved using quantified Boolean satisfiability is described. this technique is general enough to be applied to any type of logic function and programmable circuit;thus, it has many applications to FPGAs. the application demonstrated is the FPGA programmable logic block evaluation and the results show that this tool allows radical new features of FPGA logic blocks to be evaluated in a rigorous scientific way.

关键词： logic synthesis field programmable gate arrays Formal logic logic functions

来源：评论

学校读者我要写书评

暂无评论

Design space exploration of the European option benchmark using hyperstreams

Design space exploration of the European option benchmark us...

引用

17th international conference on field programmable logic and applications

作者： Morris, Gareth W. Aubury, Matt Celoxica Abingdon OX14 4RX Oxon England

ISBN: (纸本)9781424410590

the benchmark of pricing a European option via Monte Carlo simulation is commonly used in financial engineering for evaluating the performance of new computational techniques and to tune the parameters of the Monte Carlo simulation for improved convergence. this paper presents a comparison of different FPGA implementations of the European option benchmark against other implementations using GPUs, Cell BE, and a traditional software implementation. Error against a closed form solution is contrasted with relative acceleration for the different implementations. the FPGA approach gives significant performance advantages compared to the alternatives examined. An acceleration of x compared to a reference software implementation can be obtained using FPGAs, compared to only x in the case of the best non-FPGA alternative. Better error performance than a double precision floating point software implementation may also be obtained. In addition, the reconfigurability of an FPGA solution allows tradeoffs between acceleration and error not possible with alternative approaches. the FPGA implementations were produced using 'HyperStreams', a high level abstraction for designing arithmetic pipelines built on the Handel-C programming language.

关键词： field programmable gate arrays (FPGA)

来源：评论

学校读者我要写书评

暂无评论

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案：

请选择收藏分类：

通借通还

建议与咨询 留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案： 新增检索档案 确定 取消

请选择收藏分类： 新增自定义分类 确定 取消

通借通还

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

请选择保存的检索档案：

请选择收藏分类：