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检索条件"任意字段=17th International Conference on Parallel and Distributed Computing Systems, PDCS 2004"

共 281 条记录，以下是71-80 订阅

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A parallel implementation of an XDraw viewshed algorithm with spark 21

A parallel implementation of an XDraw viewshed algorithm wit...

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21st IEEE international conference on High Performance computing and Communications, 17th IEEE international conference on Smart City and 5th IEEE international conference on Data Science and systems, HPCC/SmartCity/DSS 2019

作者： Jianbo, Zhang Caikun, Chen Tingnan, Liang Hao, Xia Simin, Zhou Faculty of Information Engineering China University of Geosciences Wuhan China

ISBN: (纸本)9781728120584

Viewshed analysis is an indispensable part of digital terrain analysis and is widely used in many application domains. High-resolution raster DEM data bring significant computational challenges to the existing viewshed analysis algorithms, which are computationally intensive and require a large memory space and massive computing power. the viewshed analysis process can be accelerated through the use of Apache Spark. In this article, we present both a tile-based raster data storing strategy and an equal-volume computing strategy for distributed viewshed computation using Spark. the parallel implementation of the XDraw algorithm mainly consists of three parts: (1) partitioning a raster DEM file into square tile sets and reorganizing these tile sets to prevent tile overlap across data divisions of HDFS, (2) subdividing the DEM into multiple equal-volume data sectors according to the viewpoint position, and (3) retrieving the corresponding tile sets of each sector to perform the XDraw algorithm independently and efficiently. Experiments with realworld datasets show that the two proposed strategies can achieve higher speed-up and efficiency for XDraw viewshed analysis as the raster DEM data volume is dramatically increased. © 2019 IEEE.

关键词： Sparks Partitioning algorithms distributed databases Graphics processing units Geology parallel processing Approximation algorithms

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Flexible Linear Algebra Development and Scheduling with Cholesky Factorization 17

Flexible Linear Algebra Development and Scheduling with Chol...

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2015 IEEE 17th international conference on High Performance computing and Communications (HPCC)

作者： Haidar, Azzam YarKhan, Asim Cao, Chongxiao Luszczek, Piotr Tomov, Stanimire Dongarra, Jack Univ Tennessee Knoxville TN 37996 USA Oak Ridge Natl Lab Oak Ridge TN USA Univ Manchester Manchester M13 9PL Lancs England

ISBN: (纸本)9781479989379

Modern high performance computing environments are composed of networks of compute nodes that often contain a variety of heterogeneous compute resources, such as multicore CPUs and GPUs. One challenge faced by domain scientists is how to efficiently use all these distributed, heterogeneous resources. In order to use the GPUs effectively, the workload parallelism needs to be much greater than the parallelism for a multicore-CPU. Additionally, effectively using distributed memory nodes brings out another level of complexity where the workload must be carefully partitioned over the nodes. In this work we are using a lightweight runtime environment to handle many of the complexities in such distributed, heterogeneous systems. the runtime environment uses task-superscalar concepts to enable the developer to write serial code while providing parallel execution. the task-programming model allows the developer to write resource-specialization code, so that each resource gets the appropriate sized workload-grain. Our task-programming abstraction enables the developer to write a single algorithm that will execute efficiently across the distributed heterogeneous machine. We demonstrate the effectiveness of our approach with performance results for dense linear algebra applications, specifically the Cholesky factorization.

关键词： Cholesky factorization accelerator-based distributed memory computers superscalar dataflow scheduling heterogeneous HPC computing

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A characterization methodology for parallel systems benchmarks 17

A characterization methodology for parallel systems benchmar...

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17th international conference on parallel and distributed computing systems

作者： Cremonesi, P Muttoni, L Serazzi, G Politecn Milan Dipartimento Elettr & Informaz I-20133 Milan Italy

ISBN: (纸本)1880843528

Even though benchmarks can be used in all types of performance evaluation studies, their principal field of application is in competitive procurement studies. Benchmarking is widely used in the performance evaluation and procurement studies of parallel systems. In such systems the interactions between the parallel program structures and the hardware components are very complex and specific metrics are required to capture the matching between software and hardware elements. In order to obtain reliable and useful results from the execution of a benchmark suite on a given machine two main conditions should be satisfied: the benchmark must be widely used to evaluate the parallel machines of different vendors and the characteristics of the workload generated by its execution should be known. the popularity of a benchmark allows for the availability of a large set of results that are fundamental for the comparison of the performance of the considered system with those of the competitors. the knowledge about the characteristics of a benchmark in terms of the utilization of the resources that mostly influence the performance of a parallel system (e.g., memory size, communication bandwidth, processor time) is helpful in order to understand the results obtained from its execution and to motivate the difference between systems. In this paper a methodology for the characterization of benchmarks for parallel machines is proposed. An experimental validation of the methodology applicability to real parallel benchmarks, namely the NAS parallel Benchmarks suite, is described.

关键词： Benchmarking

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Integration of existing IEC 61131-3 systems in an IEC 61499 distributed solution

Integration of existing IEC 61131-3 systems in an IEC 61499 ...

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17th IEEE international conference on Emerging Technologies and Factory Automation (ETFA)

作者： Campanelli, Stefano Foglia, Pierfrancesco Prete, Cosimo Antonio Univ Pisa Dipartimento Ingn Informaz I-56126 Pisa Italy

ISBN: (纸本)9781467347372;9781467347358

the IEC 61499 standard allows to model and design new generation control systems, providing innovative concepts of software engineering (such as abstraction, encapsulation, reuse) to the world of control engineering. the industrial reception of the standard, however, is still in an early stage, also because its introduction results in the adoption of a programming paradigm profoundly different than the widespread IEC 61131-3. this paper presents a method for the integration of the two standards, that allows to exploit the benefits of both. the proposed architecture is based on the parallel execution of both environments that interact with each other through some specific interfaces. A test implementation of the architecture is also presented to demonstrate the feasibility of the proposed solution.

关键词： IEC standards application program interfaces control system synthesis distributed control industrial control manufacturing systems parallel programming peripheral interfaces production engineering computing programmable controllers software engineering

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Study of Solid State Drives performance in PROOF distributed analysis system

Study of Solid State Drives performance in PROOF distributed...

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17th international conference on computing in High Energy and Nuclear Physics (CHEP)

作者： Panitkin, S. Y. Ernst, M. Petkus, R. Rind, O. Wenaus, T. Brookhaven Natl Lab Upton NY 11973 USA

Solid State Drives (SSD) is a promising storage technology for High Energy Physics parallel analysis farms. Its combination of low random access time and relatively high read speed is very well suited for situations where multiple jobs concurrently access data located on the same drive. It also has lower energy consumption and higher vibration tolerance than Hard Disk Drive (HDD) which makes it an attractive choice in many applications raging from personal laptops to large analysis farms. the parallel ROOT Facility-PROOF is a distributed analysis system which allows to exploit inherent event level parallelism of high energy physics data. PROOF is especially efficient together with distributed local storage systems like Xrootd, when data are distributed over computing nodes. In such an architecture the local disk subsystem I/O performance becomes a critical factor, especially when computing nodes use multi-core CPUs. We will discuss our experience with SSDs in PROOF environment. We will compare performance of HDD with SSD in I/O intensive analysis scenarios. In particular we will discuss PROOF system performance scaling with a number of simultaneously running analysis jobs.

关键词： Energy utilization

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A space-efficient parallel algorithm for computing betweenness centrality in distributed memory

A space-efficient parallel algorithm for computing betweenne...

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17th international conference on High Performance computing, HiPC 2010

作者： Edmonds, Nick Hoefler, Torsten Lumsdaine, Andrew Open Systems Laboratory Indiana University Bloomington IN 47405 United States National Center of Supercomputing Applications University of Illinois at Urbana-Champaign Urbana IL 61801 United States

ISBN: (纸本)9781424485185

Betweenness centrality is a measure based on shortest paths that attempts to quantify the relative importance of nodes in a network. As computation of betweenness centrality becomes increasingly important in areas such as social network analysis, networks of interest are becoming too large to fit in the memory of a single processing unit, making parallel execution a necessity. parallelization over the vertex set of the standard algorithm, with a final reduction of the centrality for each vertex, is straightforward but requires Ω(|V|2) storage. In this paper we present a new parallelizable algorithm with low spatial complexity that is based on the best known sequential algorithm. Our algorithm requires O(|V| + |E|) storage and enables efficient parallel execution. Our algorithm is especially well suited to distributed memory processing because it can be implemented using coarse-grained parallelism. the presented time bounds for parallel execution of our algorithm on CRCW PRAM and on distributed memory systems both show good asymptotic performance. Experimental results with a distributed memory computer show the practical applicability of our algorithm. ©2010 IEEE.

关键词： Memory architecture

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A parallel algorithm for statistical multiword term extraction from very large corpora 17

A parallel algorithm for statistical multiword term extracti...

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2015 IEEE 17th international conference on High Performance computing and Communications (HPCC)

作者： Goncalves, Carlos Silva, Joaquim F. Cunha, Jose C. IPL ISEL P-1959007 Lisbon Portugal Univ Nova Lisboa Fac Ciencias & Tecnol NOVA Lab Comp Sci & Informat P-2829516 Caparica Portugal

ISBN: (纸本)9781479989379

Multi-word Relevant Expressions (REs) can be defined as sequences of words (n-grams) with strong semantic meaning, such as "ice melting" and "Ministere des Affaires Etrangeres", useful in Information Retrieval, Document Clustering or Classification and Indexing of Documents. the need of extracting REs in several languages led research on statistical approaches rather than symbolic methods, since the former allow language-independence. Based on the assumption that REs have strong cohesion between their consecutive n-grams, the LocalMaxs algorithm is a language independent approach that extracts REs. Apart from its good precision, this extractor is time-consuming, being inoperable for Big Data if implemented in a sequential manner. this paper presents the first parallel and distributed version of this algorithm, achieving almost linear speedup and sizeup when processing corpora up to 1 billion words, using up to 54 virtual machines in a public cloud. this parallel version of the algorithm explores the statistical knowledge of the n-grams in the corpus, to promote the locality of the references.

关键词： Text Mining Large Corpora Multiword Terms Statistical Extraction parallel Processing Cloud

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parallel computing Technologies - 17th international conference, PaCT 2023, Proceedings

Parallel Computing Technologies - 17th International Confere...

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parallel computing Technologies - 17th international conference, PaCT 2023, Proceedings

ISBN: (纸本)9783031416729

the proceedings contain 15 papers. the special focus in this conference is on parallel computing Technologies. the topics include: parallel Generation and Analysis of Optimal Chordal Ring Networks Using Python Tools on Kunpeng Processors;Combinatorial Aspect of Code Restructuring for Virtual Memory Computer systems Under WS Swapping Strategy;probabilistic Resources Allocation with Group Dependencies in distributed computing;multicriteria Task Distribution Problem for Resource-Saving Data Processing;scheduling of Workflows with Task Resource Requirements in Cluster Environments;Verifying the Correctness of HPC Performance Monitoring Data;automatic parallelization of Iterative Loops Nests on distributed Memory computing systems;didal: distributed Data Library for Development of parallel Fragmented Programs;Trace Balancing Technique for Trace Playback in LuNA System;Case Study for Running Memory-Bound Kernels on RISC-V CPUs;pair of Genes: Technical Validation of distributed Causal Role Attribution to Gene Network Expansion;HiTViSc: High-throughput Virtual Screening as a Service;expanding the Cellular Automata Topologies Library for parallel Implementation of Synchronous Cellular Automata.

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Phoenix: A Runtime Environment for High Performance computing on Chip Multiprocessors

Phoenix: A Runtime Environment for High Performance Computin...

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17th Euromicro international conference on parallel, distributed and Network-Based Processing

作者： Pant, Avneesh Jafri, Hassan Kindratenko, Volodymyr Univ Illinois NCSA Urbana IL 61801 USA

ISBN: (纸本)9780769535449

Execution of applications on upcoming high-performance computing (HPC) systems introduces a variety of new challenges and amplifies many existing ones. these systems will be composed of a large number of "fat" nodes, where each node consists of multiple processors on a chip with symmetric multithreading capabilities, interconnected via high-performance networks. Traditional system software for parallel computing considers these chip multiprocessors (CMPs) as arrays of symmetric multiprocessing cores, when in fact there are fundamental differences among them. Opportunities for optimization on CMPs are lost using this approach. We show that support for fine-grained parallelism coupled with an integrated approach for scheduling of compute and communication tasks is required for efficient execution on this architecture. We propose Phoenix, a runtime system designed specifically for execution on CMP architectures to address the challenges of performance and programmability for upcoming HPC systems. An implementation of message passing interface (MPI) atop Phoenix is presented. Micro-benchmarks and a production MPI application are used to highlight the benefits of our implementation vis-A-vis traditional MPI implementations on CMP architectures.

关键词： runtime chip multiprocesors MPI

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Reflex Barrier: A Scalable Network-Based Synchronization Barrier

Reflex Barrier: A Scalable Network-Based Synchronization Bar...

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17th IEEE international conference on parallel and distributed systems (ICPADS)

作者： Anbar, Ahmad Serres, Olivier El-Ghazawi, Tarek George Washington Univ NSF Ctr High Performance Reconfigurable Comp CHRE Dept Elect & Comp Engn Washington DC 20052 USA

ISBN: (纸本)9780769545769

High-performance computing is witnessing the proliferation of multi-core processors in parallel architectures, and the trend is expected to increase further with the emerging many-core technology, leading to hundreds of processing cores within each compute node in the near future. Along side with this trend, it is also clear that total number of cores within the whole system is increasing. To be able to harvest the fruits of this massive parallelism, inter-process synchronization and communication should be as lightweight as they can be, and should be relying on as limited involvement as possible of the participating processors/cores. the synchronization algorithms that target shared memory processors are expected not to be able to scale on many-cores as they rely on atomics, locks, and/or cache coherence protocols, which all should be very costly operations on many-cores. In the same time, some many-core architectures provide user space networks on chip (NoCs) that operate similar to regular networks. In this paper, we are introducing the Reflex barrier, a new synchronization barrier algorithm that relies on fundamental networking concepts. As the barrier relies on the characteristics of the network, it requires very little intervention from the participating processors/cores. the algorithm can also be implemented as split phase, which furnish an opportunity to reduce the synchronization cost. We implemented the algorithm using Unified parallel C (UPC), MPI and pthreads. We tested our implementation on TILE64, a 64-core processor. the performance of the Reflex barrier is also analyzed and compared to other algorithms using performance models.

关键词： Reflex barrier Synchronization barrier Many-cores distributed memory barrier Many-core clusters

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