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17th international workshop on design and architecture for signal and image processing, dasip 2024

ISBN: (纸本)9783031628733

the proceedings contain 9 papers. the special focus in this conference is on design and architecture for signal and image processing. the topics include: sEMG-Based Gesture Recognition with Spiking Neural Networks on Low-Power FPGA;A Highly Configurable Platform for Advanced PPG Analysis;preface;Standalone Nested Loop Acceleration on CGRAs for signal processing Applications;optimising Graph Representation for Hardware Implementation of Graph Convolutional Networks for Event-Based Vision;Improving the Energy Efficiency of CNN Inference on FPGA Using Partial Reconfiguration;scratchy: A Class of Adaptable architectures with Software-Managed Communication for Edge Streaming Applications.

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15th international workshop on design and architecture for signal and image processing, dasip 2022, held jointly with the 17th international Conference on High-Performance Embedded architectures and Compilers, HiPEAC 2022

15th International Workshop on Design and Architecture for S...

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15th international workshop on design and architecture for signal and image processing, dasip 2022, held jointly with the 17th international Conference on High-Performance Embedded architectures and Compilers, HiPEAC 2022

ISBN: (纸本)9783031127472

the proceedings contain 13 papers. the special focus in this conference is on design and architecture for signal and image processing. the topics include: Exploring Fully Convolutional Networks for the Segmentation of Hyperspectral Imaging Applied to Advanced Driver Assistance Systems;an Adaptable Cognitive Microcontroller Node for Fitness Activity Recognition;towards Real-Time and Energy Efficient Siamese Tracking – A Hardware-Software Approach;Low Latency architecture design for Decoding 5G NR Polar Codes;Efficient Software and Hardware Implementations of a QCSP Communication System;Dynamic Pruning for Parsimonious CNN Inference on Embedded Systems;DL-CapsNet: A Deep and Light Capsule Network;Comparative Study of Scheduling a Convolutional Neural Network on Multicore MCU;influence of Dataflow Graph Moldable Parameters on Optimization Criteria;QoS Aware design-Time/Run-Time Manager for FPGA-Based Embedded Systems;fixed-Point Code Synthesis Based on Constraint Generation.

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An Initial Framework for Prototyping Radio-Interferometric Imaging Pipelines 17th

An Initial Framework for Prototyping Radio-Interferometric I...

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17th international workshop on design and architecture for signal and image processing (dasip)

作者： Wang, Sunrise Gac, Nicolas Miomandre, Hugo Nezan, Jean-Francois Desnos, Karol Orieux, Francois Univ Paris Saclay Lab Signaux & Syst CentraleSupelec CNRS F-91190 Gif Sur Yvette France Univ Rennes CNRS INSA Rennes IETR UMR 6164 F-35000 Rennes Ille & Vilaine France

ISBN: (纸本)9783031628733;9783031628740

Although large radio-telescope arrays allow us to observe the celestial sphere with an unprecedented level of detail and sensitivity, additional antennas drastically increases the cost of processing and storing their data, complicating the design of computing hardware. Our overall goal is to provide a system, which we term SimSDP, to aid in their design. It will achieve this by providing resource usage estimations for some given imaging pipeline and hardware architecture, allowing for more informed decisions when building the production systems. We lay the groundworks in this paper by presenting and validating an initial system that implements three different imaging pipelines. We find that in most cases, our system is able to accurately estimate the scaling across both algorithmic parameters as well as parallelization when compared to measured data, with errors roughly in the 1-5% range, demonstrating its ability to inform design decisions.

关键词： Algorithm design Space Exploration SKAO PREESM Radio-Interferometry Resource Estimation

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A Highly Configurable Platform for Advanced PPG Analysis 17th

A Highly Configurable Platform for Advanced PPG Analysis

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17th international workshop on design and architecture for signal and image processing (dasip)

作者： De Gevigney, Flavie Durand Heulot, Julien Bazin, Eric Nezan, Jean-Francois Dardaillon, Mickael Aridhi, Slaheddine Univ Rennes INSA Rennes CNRS IETR UMR6164 Rennes France Sensoria Analyt Valbonne France

ISBN: (纸本)9783031628733;9783031628740

Growing interest in healthcare applications has made biomedical engineering one of the fastest growing disciplines in recent years. Photoplethysmography (PPG) is one of these trends since PPG sensors are embedded into many devices like smartwatches or oximeters. Due to the versatility of PPG, it is the technique of choice for the non-invasive monitoring of vital signs such as heart rate, respiratory rate, blood oxygen saturation and blood pressure. However, commercial pulse oximeters often use proprietary data acquisition and visualization techniques, making digital signal processing on raw data difficult or impossible. this paper presents a hardware platform for the exploration of new biological signal analysis based on PPG. the originality of the platform is to expand the number of wavelengths to 8 and to allow the parameterization of the acquisition by choosing the sample rate. this allows the PPG sensor to be adapted to the needs of analysis on the whole signal or perform high precision measurements. Much consideration has been given to the accurate data acquisition during sports activities.

关键词： Photoplethysmography PPG Multi-wavelength Mixed signal Heart Rate SpO2

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Standalone Nested Loop Acceleration on CGRAs for signal processing Applications 17th

Standalone Nested Loop Acceleration on CGRAs for Signal Proc...

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17th international workshop on design and architecture for signal and image processing (dasip)

作者： Sunny, Chilankamol Das, Satyajit Martin, Kevin J. M. Coussy, Philippe IIT Palakkad Kanjikode Kerala India Univ Bretagne Sud UMR 6285 Lab STICC F-56100 Lorient France

ISBN: (纸本)9783031628733;9783031628740

Coarse-Grained Reconfigurable Array (CGRA) architectures are becoming increasingly popular as low-power accelerators in compute and data intensive application domains such as security, multimedia, signal processing, and machine learning. the efficiency of a CGRA is determined by its architectural features and the compiler's ability to exploit the spatio-temporal configuration. Numerous design optimizations and mapping techniques have been introduced in this direction. However, the execution model has been overlooked, despite its critical role in ensuring the efficient acceleration of applications. Most of the existing CGRA implementations follow a hosted approach i.e., they execute the modulo scheduled innermost loop, entrusting outer loops to the host processor. this increases synchronization overhead with the host, mitigating the benefits of acceleration provided by the CGRA. In this paper, we propose a compilation flow that supports efficient standalone execution of nested loops. Experiments show that the standalone execution model leads to a maximum of 12.33x and an average of 6.75x performance improvement compared to the existing hosted execution model. In the proposed model, energy consumption is reduced up to 14.49x compared to that of the hosted one. We also compared our results with state-of-the-art standalone execution that uses loop flattening and achieved a maximum of 4.80x speed up with an average of 2.80x.

关键词： Coarse grained reconfigurable array (CGRA) Nested loop acceleration Standalone execution model

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Improved Avalanche Triode First-Order Gauss Pulse Miniature Circuit Board design for Biomedical Imaging 17

Improved Avalanche Triode First-Order Gauss Pulse Miniature ...

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17th international Congress on image and signal processing, BioMedical Engineering and Informatics, CISP-BMEI 2024

作者： Li, Zhiqiang Chen, Hao Wang, Jingjing School of Physics and Electronics Shandong Normal University Jinan China

ISBN: (纸本)9798331507398

In recent years, ultra-wideband microwave medical imaging technology has gradually emerged with its advantages of low radiation and non-invasive. the current imaging equipment, however, is bulky, and the design requirements for ultra-wideband pulses in RF systems are exceedingly demanding. this manuscript delineates the development of a 35×35×1.6 mm^3 first-order Gaussian pulse generator tailored for ultra-wideband applications. the architecture of the circuit encompasses a crystal oscillator module, an amplification stage, a differential component, and a triggering mechanism. By optimizing the circuit topology using avalanche transistors and adjusting the component parameters, a first-order Gaussian pulse was successfully produced on an FR-4 substrate, exhibiting a pulse duration of 1.5 ns, a peak-to-peak amplitude of 14 V, and a half-peak full-width of 0.5 ns. Experimental results validate the pulse generator's compliance with the necessary ultra-wideband characteristics. © 2024 IEEE.

关键词： Crystal oscillators

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Automated Deep Learning Models for Medical image Segmentation and Denoising 17

Automated Deep Learning Models for Medical Image Segmentatio...

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17th international Conference on signal processing and Communication Systems, ICSPCS 2024

作者： Rajesh, Chilukamari Sadam, Ravichandra Kumar, Sushil Andhra Pradesh Amaravati522237 India National Institute of Technology Department of Computer Science and Engineering Telangana Warangal506004 India National Institute of Technology Department of Computer Engineering Haryana Kurukshetra136119 India

ISBN: (纸本)9798350389630

Medical image segmentation plays a critical role in diagnosing and treating disease;it is a challenging task due to the complexity and variety of medical images. One of the critical factors in enhancing the accuracy and reliability of segmentation results is denoising, which involves removing noise from input images. Deep Neural Networks (DNNs) have shown promising results in medical image segmentation, but the manual design of DNN models is time-consuming and requires domain knowledge. To address this problem, Neural architecture Search (NAS) provides an automated approach for developing neural network structures, eliminating manual design requirements. this paper introduces two evolutionary DNN models for medical image denoising and segmentation. the denoising model serves as a preprocessing step for segmentation, enabling us to assess its impact on medical image segmentation performance compared to normal images. the proposed approach performed well, with Dice scores of 86.99% and 88.62% on the original images for the Spleen and Heart segmentation datasets, respectively. While it achieved Dice scores of 89.12% and 87.78% on denoised images for the Heart and Spleen segmentation datasets, respectively. the experimental findings show that the architecture derived from the proposed approach outperforms existing models. © 2024 IEEE.

关键词： image denoising

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On Cache Limits for Dataflow Applications and Related Efficient Memory Management Strategies 21

On Cache Limits for Dataflow Applications and Related Effici...

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14th workshop on design and architectures for signal and image processing, dasip 2021, held jointly with the 16th HiPEAC Conference

作者： Ghasemi, Alemeh Cataldo, Rodrigo Diguet, Jean-Philippe Martin, Kevin J. M. Université de Bretagne-Sud France

ISBN: (纸本)9781450389013

the dataflow paradigm frees the designer to focus on the functionality of an application, independently from the underlying architecture executing it. While mapping the dataflow computational part to the cores seems obvious, the memory aspects do not match accordingly. Dataflow compilers usually do not consider the presence of caches when generating code. A generally accepted idea is that bigger and multi-level caches improve the performance of applications. Unfortunately, state-of-the-art dataflow compilers may prove the exception to this rule. this paper presents two efficient memory management strategies for dataflow applications through a study on the impact of sharing, size, and the number of levels of caches on them. the results show that bigger is not always better, and the foreseen future of more cores and bigger caches do not guarantee software-free better performance for dataflow applications. We propose two strategies, that can be used concurrently, to address the memory aspects of the dataflow model: copy-on-write and non-temporal memory transfers. Experimental results show that we speed up a computer stereo vision application by 2.1 × and reduce the number of L1 data cache misses by 45% while maintaining the actors' source code and design intact. © 2021 ACM.

关键词： Stereo image processing

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High-speed readout system of X-ray CMOS image sensor for time domain astronomy

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JOURNAL OF INSTRUMENTATION 2024年第1期19卷 C01006页

作者： Ogino, Naoki Arimoto, Makoto Sawano, Tatsuya Yonetoku, Daisuke Shen, Hsien-chieh Sakamoto, Takanori Hiraga, Junko S. Yatsu, Yoichi Mihara, Tatehiro Kanazawa Univ Kanazawa Ishikawa Japan Aoyama Gakuin Univ 5-10-1 FuchinobeChuo Ku Sagamihara Kanagawa Japan Kwansei Gakuin Univ 2-2 Gakuen Sanda Hyogo Japan Tokyo Inst Technol 2-12-1 OokayamaMeguro Ku Tokyo Japan Inst Phys & Chem Res RIKEN 2-1 Hirosawa Wako Saitama 3510198 Japan

We developed an FPGA-based high-speed readout system for a complementary metal-oxide -semiconductor (CMOS) image sensor to observe soft X-ray transients in future satellite missions, such as HiZ-GUNDAM. Our previous research revealed that the CMOS image sensor has low-energy X-ray detection capability (0.4-4 keV) and strong radiation tolerance, which satisfies the requirements of the HiZ-GUNDAM mission. However, CMOS sensors typically have small pixel sizes (e.g., similar to 10 mu m), resulting in large volumes of image data. GSENSE400BSI has 2048x2048 pixels, producing 6 Mbyte per frame. these large volumes of observed raw image data cannot be stored in a satellite bus system with a limited storage size. therefore, only X-ray photon events must be extracted from the raw image data. Furthermore, the readout time of CMOS image sensors is approximately ten times faster than that of typical X-ray CCDs, requiring faster event extraction on a timescale of similar to 0.1 s. To address these issues, we have developed an FPGA-based image signal processing system capable of high-speed X-ray event extraction onboard without storing raw image data. the developed compact system enabled mounting on a CubeSat mission, facilitating early in-orbit operation demonstration. Here, we present the design and results of the performance evaluation tests of the proposed FPGA-based readout system. Utilizing X-ray irradiation experiments, the results of the X-ray event extraction with the onboard and offline processing methods were consistent, validating the functionality of the proposed system.

关键词： Detector control systems (detector and experiment monitoring and slow-control systems, architecture, hardware, algorithms, databases) On-board data handling On-board space electronics X-ray detectors

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Initial Implementation of LYSO-PSPMT Block Detector with an All Digital DAQ System

Initial Implementation of LYSO-PSPMT Block Detector with an ...

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IEEE Nuclear Science Symposium (NSS)/Medical Imaging Conference (MIC)/17th international workshop on Room-Temperature Semiconductor X-ray and Gamma-ray Detectors

作者： Xie, Qingguo Chen, Yuanbao Zhu, Jun Wang, Xi Liu, Jingjing Liu, Wei Jiang, Yachao Niu, Ming Wu, Zhongyi Long, Anwen Guo, Ning Xi, Daoming Xiao, Peng Gao, Junxiong Chen, Chin-Tu Wang, Yunbo Kao, Chien-Min Wuhan Natl Lab Optoelect Wuhan Hubei Peoples R China Huazhong Univ Sci & Technol Dept Control Sci & Engn Wuhan Peoples R China Huazhong Univ Sci & Technol Sch Comp Sci & Technol Wuhan Peoples R China Huazhong Univ Sci & Technol Dept Elect Sci & Engn Wuhan Peoples R China Univ Chicago Dept Radiol Chicago IL USA

ISBN: (纸本)9781424491063

An all-digital positron emission tomography (PET) scanner for imaging small animals has been developed at Huazhong University of Science and Technology (HUST). the implementation of block detector with position sensitive photomultiplier (PSPMT) and multi-voltage threshold (MVT) technology is presented in this paper. the detector comprises 12 basic detector modules (BDMs), which can be used to construct various types of PET scanner architecture due to the modularized design. Each BDM is composed of a detector unit (DU) and a digital processing unit (DPU). the scintillation pulses are obtained in DU, from which the time, energy and position can be derived and processed in DPU by using digital signal processing (DSP) algorithm. then coincidence data and list-mode data can be obtained in soft singles processing unit (SSPU). We arrange two BDMs as a dual-head PET scanner to evaluate the system. Our results show that the average energy resolution is similar to 14%@511keV full-width-at-half-maximum (FWHM) and the coincidence time determination is similar to 1.38 ns FWHM. Moreover, the reconstructed image of a homemade micro-Derenzo phantom shows that the rods with a diameter of 1.6mm can be clearly distinguished. the results are promising and demonstrate the potentials of the all-digital PET system.

关键词： Digital signal processing

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