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检索条件"任意字段=18th ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming"

共 375 条记录，以下是171-180 订阅

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Multi-Level parallel Computing of Reverse Time Migration for Seismic Imaging on Blue Gene/Q 13

Multi-Level Parallel Computing of Reverse Time Migration for...

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18th acm sigplan symposium on principles and practice of parallel programming

作者： Lu, Ligang Magerlein, Karen IBM Watson Res Ctr Yorktown Hts NY USA

ISBN: (纸本)9781450319225

Blue Gene/Q (BG/Q) is an early representative of increasing scale and thread count that will characterize future HPC systems: large counts of nodes, cores, and threads; and a rich programming environment with many degrees of freedom in parallel computing optimization. So it is both a challenge and an opportunity to it to accelerate the seismic imaging applications to the unprecedented levels that will significantly advance the technologies for the oil and gas industry. In this work we aim to address two important questions: how HPC systems with high levels of scale and thread count will perform in real applications; and how systems with many degrees of freedom in parallel programming can be calibrated to achieve optimal performance. Based on BG/Q's architecture features and RTM workload characteristics, we developed massive domain partition, MPI , and SIMD Our detailed deep analyses in various aspects of optimization also provide valuable experience and insights into how can be utilized to facilitate the advance of seismic imaging technologies. Our BG/Q RTM solution achieved a 14.93x speedup over the BG/P implementation. Our multi-level parallelism strategies for Reverse Time Migration (RTM) seismic imaging computing on BG/Q provides an example of how HPC systems like BG/Q can accelerate applications to a new level.

关键词： Multi-level parallelism parallel Computing High Performance Computing Performance Optimization Reverse Time Migration Seismic Imaging

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parallel programming with Big Operators

Parallel Programming with Big Operators

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18th acm sigplan symposium on principles and practice of parallel programming

作者： Park, Changhee Steele, Guy L., Jr. Tristan, Jean-Baptiste Korea Adv Inst Sci & Technol Taejon South Korea

In the sciences, it is common to use the so-called "big operator" notation to express the iteration of a binary operator (the reducer) over a collection of values. Such a notation typically assumes that the reducer is associative and abstracts the iteration process. Consequently, from a programming point-of-view, we can organize the reducer operations to minimize the depth of the overall reduction, allowing a potentially parallel evaluation of a big operator expression. We believe that the big operator notation is indeed an effective construct to express parallel computations in the Generate/Map/Reduce programming model, and our goal is to introduce it in programming languages to support parallel programming. the effective definition of such a big operator expression requires a simple way to generate elements, and a simple way to declare algebraic properties of the reducer (such as its identity, or its commutativity). In this poster, we want to present an extension of Scala with support for big operator expressions. We show how big operator expressions are defined and how the API is organized to support the simple definition of reducers with their algebraic properties.

关键词： parallelism Mathematical notation Scala

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the Tasks with Effects Model for Safe Concurrency 13

The Tasks with Effects Model for Safe Concurrency

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18th acm sigplan symposium on principles and practice of parallel programming

作者： Heumann, Stephen T. Adve, Vikram S. Wang, Shengjie Univ Illinois Urbana IL 61801 USA

ISBN: (纸本)9781450319225

Today's widely-used concurrent programming models either provide weak safety guarantees, making it easy to write code with subtle errors, or are limited in the class of programs that they can express. We propose a new concurrent programming model based on tasks with effects that offers strong safety guarantees while still providing the flexibility needed to support the many ways that con-currency is used in complex applications. the core unit of work in our model is a dynamically-created task. the model's key feature is that each task has programmer-specified effects, and a run-time scheduler is used to ensure that two tasks are run concurrently only if they have non-interfering effects. through the combination of statically verifying the declared effects of tasks and using an effect-aware run-time scheduler, our model is able to guarantee strong safety properties, including data race freedom and atomicity. It is also possible to use our model to write programs and computations that can be statically proven to behave deterministically. We describe the tasks with effects programming model and provide a formal dynamic semantics for it. We also describe our implementation of this model in an extended version of Java and evaluate its use in several programs exhibiting various patterns of concurrency.

关键词： Languages Verification Design Performance Tasks effects task scheduling concurrent and parallel programming task isolation data race freedom atomicity determinism

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21st century computer architecture 14

21st century computer architecture

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Proceedings of the 19th acm sigplan symposium on principles and practice of parallel programming

作者： Mark D. Hill University of Wisconsin - Madison Madison WI USA

ISBN: (纸本)9781450326568

this talk has two parts. the first part will discuss possible directions for computer architecture research, including architecture as infrastructure, energy first, impact of new technologies, and cross-layer opportunities. this part is based on a 2012 Computing Community Consortium (CCC) whitepaper effort led by Hill, as well as other recent National Academy and ISAT studies. See: http://***/ccc/docs/init/***. the second part of the talk will discuss one or more exam-ples of cross-layer research advocated in the first part. For example, our analysis shows that many "big-memory" server workloads, such as databases, in-memory caches, and graph analytics, pay a high cost for page-based virtual memory: up to 50% of execution time wasted. Via small changes to the operating system (Linux) and hardware (x86-64 MMU), this work reduces execution time these workloads waste to less than 0.5%. the key idea is to map part of a process's linear virtual address space with a new incarnation of segmentation, while providing compatibility by mapping the rest of the virtual address space with pag-ing.

关键词： computer systems performace architechture programming methods new technology energy

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ZOOMM: A parallel Web Browser Engine for Multicore Mobile Devices

ZOOMM: A Parallel Web Browser Engine for Multicore Mobile De...

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18th acm sigplan symposium on principles and practice of parallel programming

作者： Cascaval, Calin Fowler, Seth Ortego, Pablo Montesinos Piekarski, Wayne Reshadi, Mehrdad Robatmili, Behnam Weber, Michael Bhavsar, Vrajesh Qualcomm Res Silicon Valley Raleigh NC USA

We explore the challenges in expressing and managing concurrency in browsers on mobile devices. Browsers are complex applications that implement multiple standards, need to support legacy behavior, and are highly dynamic and interactive. We present ZOOMM, a highly concurrent web browser engine prototype and show how concurrency is effectively exploited at different levels: speed up computation performance, preload network resources, and preprocess resources outside the critical path of page loading. On a dual-core Android mobile device we demonstrate that ZOOMM is two times faster than the native WebKit based browser when loading the set of pages defined in the Vellamo benchmark.

关键词： parallel Browser Mobile Multicore

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Ligra: A Lightweight Graph Processing Framework for Shared Memory 13

Ligra: A Lightweight Graph Processing Framework for Shared M...

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18th acm sigplan symposium on principles and practice of parallel programming

作者： Shun, Julian Blelloch, Guy E. Carnegie Mellon Univ Pittsburgh PA 15213 USA

ISBN: (纸本)9781450319225

there has been significant recent interest in parallel frameworks for processing graphs due to their applicability in studying social networks, the Web graph, networks in biology, and unstructured meshes in scientific simulation. Due to the desire to process large graphs, these systems have emphasized the ability to run on distributed memory machines. Today, however, a single multicore server can support more than a terabyte of memory, which can fit graphs with tens or even hundreds of billions of edges. Furthermore, for graph algorithms, shared-memory multicores are generally significantly more efficient on a per core, per dollar, and per joule basis than distributed memory systems, and shared-memory algorithms tend to be simpler than their distributed counterparts. In this paper, we present a lightweight graph processing framework that is specific for shared-memory parallel/multicore machines, which makes graph traversal algorithms easy to write. the framework has two very simple routines, one for mapping over edges and one for mapping over vertices. Our routines can be applied to any subset of the vertices, which makes the framework useful for many graph traversal algorithms that operate on subsets of the vertices. Based on recent ideas used in a very fast algorithm for breadth-first search (BFS), our routines automatically adapt to the density of vertex sets. We implement several algorithms in this framework, including BFS, graph radii estimation, graph connectivity, betweenness centrality, PageRank and single-source shortest paths. Our algorithms expressed using this framework are very simple and concise, and perform almost as well as highly optimized code. Furthermore, they get good speedups on a 40-core machine and are significantly more efficient than previously reported results using graph frameworks on machines with many more cores.

关键词： Algorithms Performance Shared Memory Graph Algorithms parallel programming

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Ownership Passing: Efficient Distributed Memory programming on Multi-core Systems 13

Ownership Passing: Efficient Distributed Memory Programming ...

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18th acm sigplan symposium on principles and practice of parallel programming

作者： Friedley, Andrew Hoefler, Torsten Bronevetsky, Greg Lumsdaine, Andrew Ma, Ching-Chen Indiana Univ Bloomington IN 47405 USA ETH Zurich Switzerland Lawrence Livermore Natl Lab Livermore CA USA Rose Hulman Inst Technol Terre Haute IN 47803 USA

ISBN: (纸本)9781450319225

the number of cores in multi- and many-core high-performance processors is steadily increasing. MPI, the de-facto standard for programming high-performance computing systems offers a distributed memory programming model. MPI's semantics force a copy from one process' send buffer to another process' receive buffer. this makes it difficult to achieve the same performance on modern hardware than shared memory programs which are arguably harder to maintain and debug. We propose generalizing MPI's communication model to include ownership passing, which make it possible to fully leverage the shared memory hardware of multi-and many-core CPUs to stream communicated data concurrently with the receiver's computations on it. the benefits and simplicity of message passing are retained by extending MPI with calls to send (pass) ownership of memory regions, instead of their contents, between processes. Ownership passing is achieved with a hybrid MPI implementation that runs MPI processes as threads and is mostly transparent to the user. We propose an API and a static analysis technique to transform legacy MPI codes automatically and transparently to the programmer, demonstrating that this scheme is easy to use in practice. Using the ownership passing technique, we see up to 51% communication speedups over a standard message passing implementation on state-of-the art multicore systems. Our analysis and interface will lay the groundwork for future development of MPI-aware optimizing compilers and multi-core specific optimizations, which will be key for success in current and next-generation computing platforms.

关键词： Ownership Passing Distributed Memory Shared Memory Message Passing Multi-core

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parallel Suffix Array and Least Common Prefix for the GPU 13

Parallel Suffix Array and Least Common Prefix for the GPU

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18th acm sigplan symposium on principles and practice of parallel programming

作者： Deo, Mrinal Keely, Sean Adv Micro Devices Inc Sunnyvale CA 94088 USA Univ Texas Austin Austin TX 78712 USA

ISBN: (纸本)9781450319225

Suffix Array (SA) is a data structure formed by sorting the suffixes of a string into lexicographic order. SAs have been used in a variety of applications, most notably in pattern matching and Burrows-Wheeler Transform (BWT) based lossless data compression. SAs have also become the data structure of choice for many, if not all, string processing problems to which suffix tree methodology is applicable. Over the last two decades researchers have proposed many suffix array construction algorithm (SACAs). We do a systematic study of the main classes of SACAs with the intent of mapping them onto a data parallel architecture like the GPU. We conclude that skew algorithm [12], a linear time recursive algorithm, is the best candidate for GPUs as all its phases can be efficiently mapped to a data parallel hardware. Our OpenCL implementation of skew algorithm achieves a throughput of up to 25 MStrings/sec and a speedup of up to 34x and 5.8x over a single threaded CPU implementation using a discrete GPU and APU respectively. We also compare our OpenCL implementation against the fastest known CPU implementation based on induced copy in g and achieve a speedup of up to 3.7x. Using SA we construct BWT on GPU and achieve a speedup of 11x over the fastest known BWT on GPU. Suffix arrays are often augmented with the longest common prefix (LCP) information. We design a novel high-performance parallel algorithm for computing LCP on the GPU. Our GPU implementation of LCP achieves a speedup of up to 25x and 4.3x on discrete GPU and APU respectively.

关键词： Algorithms Performance Suffix Array Suffix Tree BWT Longest Common Prefix OpenCL GPU Prefix Sum Accelerated Processing Unit (APU)

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StreamScan: Fast Scan Algorithms for GPUs without Global Barrier Synchronization 13

StreamScan: Fast Scan Algorithms for GPUs without Global Bar...

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18th acm sigplan symposium on principles and practice of parallel programming

作者： Yan, Shengen Long, Guoping Zhang, Yunquan Chinese Acad Sci Inst Software Lab Parallel Software & Computat Sci Beijing 100864 Peoples R China Chinese Acad Sci State Key Lab Comp Sci Beijing 100864 Peoples R China Chinese Acad Sci Grad Univ Beijing 100864 Peoples R China

ISBN: (纸本)9781450319225

Scan (also known as prefix sum) is a very useful primitive for various important parallel algorithms, such as sort, BFS, SpMV, compaction and so on. Current state of the art of GPU based scan implementation consists of three consecutive Reduce-Scan-Scan phases. this approach requires at least two global barriers and 3N (N is the problem size) global memory accesses. In this paper we propose StreamScan, a novel approach to implement scan on GPUs with only one computation phase. the main idea is to restrict synchronization to only adjacent workgroups, and thereby eliminating global barrier synchronization completely. the new approach requires only 2N global memory accesses and just one kernel invocation. On top of this we propose two important optimizations to further boost performance speedups, namely thread grouping to eliminate unnecessary local barriers, and register optimization to expand the on chip problem size. We designed an auto-tuning framework to search the parameter space automatically to generate highly optimized codes for both AMD and Nvidia GPUs. We implemented our technique with OpenCL. Compared with previous fast scan implementations, experimental results not only show promising performance speedups, but also reveal dramatic different optimization tradeoffs between Nvidia and AMD GPU platforms.

关键词： Scan prefix-sum OpenCL CUDA GPU parallel algorithms

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PPoPP'12 - Proceedings of the 2012 acm sigplan symposium on principles and practice of parallel programming

PPoPP'12 - Proceedings of the 2012 ACM SIGPLAN Symposium on ...

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17th acm sigplan symposium on principles and practice of parallel programming, PPoPP'12

ISBN: (纸本)9781450311601

the proceedings contain 57 papers. the topics discussed include: scalable framework for mapping streaming applications onto multi-GPU systems;efficient performance evaluation of memory hierarchy for highly multithreaded graphics processors;extending a C-like language for portable SIMD programming;DOJ: dynamically parallelizing object-oriented programs;GPU-based NFA implementation for memory efficient high speed regular expression matching;concurrent tries with efficient non-blocking snapshots;deterministic parallel random-number generation for dynamic-multithreading platforms;algorithm-based fault tolerance for dense matrix factorizations;revisiting the combining synchronization technique;FlexBFS: a parallelism-aware implementation of breadth-first search on GPU;optimizing remote accesses for offloaded kernels: application to high-level synthesis for FPGA;and the boat hull model: adapting the roofline model to enable performance prediction for parallel computing.

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