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SPAA 2024 - Proceedings of the 36th acm symposium on parallelism in algorithms and architectures

SPAA 2024 - Proceedings of the 36th ACM Symposium on Paralle...

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36th acm symposium on parallelism in algorithms and architectures, SPAA 2024

ISBN: (纸本)9798400704161

the proceedings contain 54 papers. the topics discussed include: expediting hazard pointers with bounded RCU critical sections;Alock: asymmetric lock primitive for RDMA systems;when is parallelism fearless and zero-cost with rust?;efficient parallel reinforcement learning framework using the reactor model;parallel best arm identification in heterogeneous environments;brief announcement: lock-free learned search data structure;brief announcement: LIT: lookup interlocked table for range queries;brief announcement: a fast scalable detectable unrolled lock-based linked list;scheduling out-trees online to optimize maximum flow;optimizing dynamic data center provisioning through speed scaling: a primal-dual perspective;scheduling jobs with work-inefficient parallel solutions;and multi bucket queues: efficient concurrent priority scheduling.

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SPAA 2023 - Proceedings of the 35th acm symposium on parallelism in algorithms and architectures

SPAA 2023 - Proceedings of the 35th ACM Symposium on Paralle...

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35th acm symposium on parallelism in algorithms and architectures, SPAA 2023

ISBN: (纸本)9781450395458

the proceedings contain 47 papers. the topics discussed include: Quancurrent: a concurrent quantiles sketch;an efficient scheduler for task-parallel interactive applications;efficient synchronization-light work stealing;balanced allocations in batches: the tower of two choices;massively parallel tree embeddings for high dimensional spaces;deterministic massively parallel symmetry breaking for sparse graphs;an associativity threshold phenomenon in set-associative caches;increment - and - freeze: every cache, everywhere, all of the time;multidimensional approximate agreement with asynchronous fallback;a tight characterization of fast failover routing: resiliency to two link failures is possible;releasing memory with optimistic access: a hybrid approach to memory reclamation and allocation in lock-free programs;transactional composition of nonblocking data structures;applying hazard pointers to more concurrent data structures;and nearly optimal parallel algorithms for longest increasing subsequence.

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SPAA 2022 - Proceedings of the 34th acm symposium on parallelism in algorithms and architectures

SPAA 2022 - Proceedings of the 34th ACM Symposium on Paralle...

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34th acm symposium on parallelism in algorithms and architectures, SPAA 2022

ISBN: (纸本)9781450391467

the proceedings contain 44 papers. the topics discussed include: deterministic distributed sparse and ultra-sparse spanners and connectivity certificates;fully polynomial-time distributed computation in low-treewidth graphs;adaptive massively parallel algorithms for cut problems;preparing for disaster: leveraging precomputation to efficiently repair graph structures upon failures;the energy complexity of Las Vegas leader election;a fully-distributed peer-to-peer protocol for byzantine-resilient distributed hash tables;brief announcement: the (limited) power of multiple identities: asynchronous byzantine reliable broadcast with improved resilience through collusion;brief announcement: composable dynamic secure emulation;and robust and optimal contention resolution without collision detection.

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X-Cache : A Modular Architecture for Domain-Specific Caches 22

X-Cache : A Modular Architecture for Domain-Specific Caches

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49th IEEE/acm annual International symposium on Computer Architecture (ISCA)

作者： Sedaghati, Ali Hakimi, Milad Hojabr, Reza Shriraman, Arrvindh Simon Fraser Univ Sch Comp Sci Burnaby BC Canada

ISBN: (纸本)9781450386104

With Dennard scaling ending, architects are turning to domain-specific accelerators (DSAs). State-of-the-art DSAs work with sparse data [37] and indirectly-indexed data structures [18, 30]. they introduce non-affine and dynamic memory accesses [7, 35], and require domain-specific caches. Unfortunately, cache controllers are notorious for being difficult to architect;domain-specialization compounds the problem. DSA caches need to support custom tags, data-structure walks, multiple refills, and preloading. Prior DSAs include ad-hoc cache structures, and do not implement the cache controller. We propose X-Cache, a reusable caching idiom for DSAs. We will be open-sourcing a toolchain for both generating the RTL and programming X-Cache. there are three key ideas: i) DSA-specific Tags (Meta-tag): the designer can use any combination of fields from the DSA-metadata as the tag. Meta-tags eliminate the overhead of walking and translating metadata to global addresses. this saves energy, and improves load-to-use latency. ii) DSA-programmable walkers (X-Actions): We find that a common set of microcode actions can be used to implement the DSA-specific walking, data block, and tag management. We develop a programmable microcode engine that can efficiently realize the data orchestration. iii) DSA-portable controller (X-Routines): We use a portable abstraction, coroutines, to let the designer express walking and orchestration. Coroutines capture the block-level parallelism, remain lightweight, and minimize controller occupancy. We create caches for four different DSA families: Sparse GEMM [35, 37], GraphPulse [30], DASX [22], and Widx [18]. X-Cache outperforms address-based caches by 1.7. and remains competitive with hardwired DSAs (even 50% improvement in one case). We demonstrate that meta-tags save 26-79% energy compared to address-tags. In X-Cache, meta-tags consume 1.5-6.5% of data RAM energy and the programmable microcode adds a further 7%.

关键词： Domain-specific architectures Caches Coroutines Dataflow architectures

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Fifer: Practical Acceleration of Irregular Applications on Reconfigurable architectures 21

Fifer: Practical Acceleration of Irregular Applications on R...

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54th annual IEEE/acm International symposium on Microarchitecture (MICRO)

作者： Nguyen, Quan M. Sanchez, Daniel MIT Cambridge MA 02139 USA

ISBN: (纸本)9781450385572

Coarse-grain reconfigurable arrays (CGRAs) can achieve much higher performance and efficiency than general-purpose cores, approaching the performance of a specialized design while retaining programmability. Unfortunately, CGRAs have so far only been effective on applications with regular compute patterns. However, many important workloads like graph analytics, sparse linear algebra, and databases, are irregular applications with unpredictable access patterns and control flow. Since CGRAs map computation statically to a spatial fabric of functional units, irregular memory accesses and control flow cause frequent stalls and load imbalance. We present Fifer, an architecture and compilation technique that makes irregular applications efficient on CGRAs. Fifer first decouples irregular applications into a feed-forward network of pipeline stages. Each resulting stage is regular and can efficiently use the CGRA fabric. However, irregularity causes stages to have widely varying loads, resulting in high load imbalance if they execute spatially in a conventional CGRA. Fifer solves this by introducing dynamic temporal pipelining: it time-multiplexes multiple stages onto the same CGRA, and dynamically schedules stages to avoid load imbalance. Fifer makes time-multiplexing fast and cheap to quickly respond to load imbalance while retaining the efficiency and simplicity of a CGRA design. We show that Fifer improves performance by gmean 2.8x (and up to 5.5x) over a conventional CGRA architecture (and by gmean 17x over an out-of-order multicore) on a variety of challenging irregular applications.

关键词： CGRAs reconfigurable architectures pipeline parallelism

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Taming the Zoo: the Unified GraphIt Compiler Framework for Novel architectures 21

Taming the Zoo: The Unified GraphIt Compiler Framework for N...

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acm/IEEE 48th annual International symposium on Computer Architecture (ISCA)

作者： Brahmakshatriya, Ajay Furst, Emily Ying, Victor A. Hsu, Claire Hong, Changwan Ruttenberg, Max Zhang, Yunming Jung, Dai Cheol Richmond, Dustin Taylor, Michael B. Shun, Julian Oskin, Mark Sanchez, Daniel Amarasinghe, Saman MIT CSAIL Cambridge MA 02139 USA Univ Washington Seattle WA 98195 USA

ISBN: (纸本)9781665433334

We live in a new Cambrian Explosion of hardware devices. the end of conventional processor scaling has driven research and industry practice to explore a new generation of approaches. the old DNA of architecture design, including vectors, threads, shared or private memories, coherence or message passing, dataflow or von Neumann execution, are hybridized together in new and exciting ways. Each new architecture exposes a unique hardware-level API. Performance and energy efficiency are critically dependent on how well programs can use these APIs. One approach is to implement custom libraries for each new hardware architecture and application domain. A more scalable approach is to utilize a portable compiler infrastructure tailored to the application domain that makes it easy to generate efficient code for a diverse set of architectures with minimal porting effort. We propose the Unified GraphIt Compiler framework (UGC), which does exactly this for graph applications. UGC achieves portability with reasonable effort by decoupling the architecture-independent algorithm from the architecture-specific schedules and backends. We introduce a new domain-specific intermediate representation, GraphlR, that is key to this decoupling. GraphIR encodes high-level algorithm and optimization information needed for hardware-specific code generation, making it easy to develop different backends (GraphVMs) for diverse architectures, including CPUs, GPUs, and next-generation hardware such as Swarm and the HammerBlade manycore. We also build scheduling language extensions that make it easy to expose optimization decisions like load balancing strategies, blocking for locality, and other data structure choices. We evaluate UGC on five algorithms and 10 input graphs on these 4 distinct architectures and show that UGC enables implementing optimizations that can provide up to 53 x speedup over programmer-generated straightforward implementations.

关键词： Compilers for Novel architectures Domain-Specific Languages Graphs Intermediate Representations

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annual acm symposium on parallelism in algorithms and architectures

Annual ACM symposium on parallelism in algorithms and archit...

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30th acm symposium on parallelism in algorithms and architectures, SPAA 2018

ISBN: (纸本)9781450357999

the proceedings contain 47 papers. the topics discussed include: parallel minimum cuts in near-linear work and low depth;trees for vertex cuts, hypergraph cuts and minimum hypergraph bisection;dynamic representations of sparse distributed networks: a locality-sensitive approach;constant-depth and subcubic-size threshold circuits for matrix multiplication;integrated model, batch, and domain parallelism in training neural networks;brief announcement: on approximating pagerank locally with sublinear query complexity;brief announcement: coloring-based task mapping for dragonfly systems;brief announcement: parallel transitive closure within 3D crosspoint memory;and lock-free contention adapting search trees.

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A Network Selection Algorithm for supporting Drone Services in 5G Network architectures 18

A Network Selection Algorithm for supporting Drone Services ...

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18th annual Wireless Telecommunications symposium (WTS)

作者： Skondras, Emmanouil Zoumi, Eirini Michalas, Angelos Vergados, Dimitrios D. Univ Piraeus Dept Informat Piraeus Greece Technol Educ Inst Western Macedonia Dept Informat Engn Kastoria Greece

ISBN: (纸本)9781538683804

Flying Ad-hoc Networks (FANETs) use 5G network access technologies to fulfill the requirements of their services. In this environment, Drone to Infrastructure (D21) communication is supported, while each drone could use both Disaster Management (DM) and non-Disaster Management (nDM) services. Efficient network selection algorithms are required to satisfy the constraints of the used services, since the presence of DM services affects the importance of nDM services in situations where a natural disaster occurs. this paper proposes a network selection algorithm which is called Dynamic Trapezoidal Fuzzy Topsis with Adaptive Criteria Weights (DTFT-ACW). DTFT-ACW accomplishes the ranking of the candidate networks considering the importance of each service, as well as the weights of the corresponding selection criteria, as they are obtained with respect to the severity level of a natural disaster occurred. Interval-Valued Trapezoidal Fuzzy Numbers (IVTFN) are used for the criteria evaluation. Experimental results show that the suggested method outperforms existing algorithms by satisfying the constraints of DM services when a disaster becomes severe. Furthermore, DTFT-ACW eliminates the computational complexity of the network selection by considering past decisions.

关键词： 5G mobile communication systems

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annual acm symposium on parallelism in algorithms and architectures

Annual ACM Symposium on Parallelism in Algorithms and Archit...

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29th acm symposium on parallelism in algorithms and architectures, SPAA 2017

ISBN: (纸本)9781450345934

the proceedings contain 45 papers. the topics discussed include: randomized composable coresets for matching and vertex cover;almost optimal streaming algorithms for coverage problems;bicriteria distributed submodular maximization in a few rounds;on energy conservation in data centers;asymptotically optimal approximation algorithms for coflow scheduling;online flexible job scheduling for minimum span;minimizing total weighted flow time with calibrations;brief announcement: scheduling parallelizable jobs online to maximize throughput;brief announcement: a new improved bound for coflow scheduling;and a communication-avoiding parallel algorithm for the symmetric eigenvalue problem.

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annual acm symposium on parallelism in algorithms and architectures

Annual ACM Symposium on Parallelism in Algorithms and Archit...

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28th acm symposium on parallelism in algorithms and architectures, SPAA 2016

ISBN: (纸本)9781450342100

the proceedings contain 52 papers. the topics discussed include: randomized approximate nearest neighbor search with limited adaptivity;encoding short ranges in TCAM without expansion: efficient algorithm and applications;extending the nested parallel model to the nested dataflow model with provably efficient schedulers;latency-hiding work stealing: scheduling interacting parallel computations with work stealing;provably good and practically efficient parallel race detection for fork-join programs;dynamic determinacy race detection for task parallelism with futures;RUBIC: online parallelism tuning for co-located transactional memory applications;investigating the performance of hardware transactions on a multi-socket machine;parallel algorithms for asymmetric read-write costs;general profit scheduling and the power of migration on heterogeneous machines;the power of migration in online machine minimization;fair online scheduling for selfish jobs on heterogeneous machines;scheduling parallelizable jobs online to minimize the maximum flow time;clairvoyant dynamic bin packing for job scheduling with minimum server usage time;parallel equivalence class sorting: algorithms, lower bounds, and distribution-based analysis;and parallel approaches to the string matching problem on the GPU.

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