Two process flows for the fabrication of stencil masks have been developed. the PN Wafer Flow- and the SOI Wafer Flow Process. Membranes and stencil masks out of different 6" Si base wafers with 3 mu m membrane t...
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ISBN:
(纸本)0819431397
Two process flows for the fabrication of stencil masks have been developed. the PN Wafer Flow- and the SOI Wafer Flow Process. Membranes and stencil masks out of different 6" Si base wafers with 3 mu m membrane thickness and a membrane diameter between 120mm and 126mm were fabricated. the membrane stress depending on the material property and doping level has been determined. First metrology measurements have been carried out.
the requirements of the 0.18 mu m and 0.25 mu m technologies lead to advanced specifications for the mask making technology in terms of pattern placement metrology, tighter than 52nm (3s) for the 0.25 mu m generation ...
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ISBN:
(纸本)0819431397
the requirements of the 0.18 mu m and 0.25 mu m technologies lead to advanced specifications for the mask making technology in terms of pattern placement metrology, tighter than 52nm (3s) for the 0.25 mu m generation and around 35nm (3s) for the next 0.18 mu m generation. In addition, the tremendous demand regarding cycle time reduction, performance to delivery schedule, and technical complexity on products impose to the mask manufacturer like Dupont Photomasks Inc. (DPI) the necessity to mix and match products between all the DPI sites. From this perspective, the matching of all the pattern placement metrology tools of all DPI production sites is mandatory. In order to control the tight specifications, the strategy for metrology is to implement a unique grid for registration on a world wide base at DPI and to calibrate all metrology tools and all writing tools to this standard grid. All investigations were performed on the LEICA LMS IPRO tools using the new correction software from Leica Microsystems.
Two process flows for the fabrication of stencil masks have been developed. the PN Wafer Flow- and the SOI Wafer Flow Process. Membranes and stencil masks out of different 6 inches Si base wafers with 3 μm membrane t...
详细信息
Two process flows for the fabrication of stencil masks have been developed. the PN Wafer Flow- and the SOI Wafer Flow Process. Membranes and stencil masks out of different 6 inches Si base wafers with 3 μm membrane thickness and a membrane diameter between 120 mm and 126 mm were fabricated. the membrane stress depending on the material property and doping level has been determined. First metrology measurements have been carried out.
Since Production started at the Photronics site in Manchester, England, mask writing capability had been centred on laser based technology (Etec CORE/ALTA toolsets). the Manchester site has now taken delivery of it...
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ISBN:
(纸本)0819431397
Since Production started at the Photronics site in Manchester, England, mask writing capability had been centred on laser based technology (Etec CORE/ALTA toolsets). the Manchester site has now taken delivery of it's first e-beam system: the ZBA 31H+, manufactured by Leica Microsystems Lithography GMBH. the ZBA 31H+ system was designed for the production of reticles utilizing 250 nanometer design technology and is expected to play a key role in Photronics' future reticle development. the addition of an e-beam system to the current laser based technology, in this instance, has been driven by increasing customer demand and the requirement for reticles containing high resolution OPC structures. the ZBA 31H+ is a variable shaped spot, vector scan electron beam lithography system operating at 20 keV. Enhancements from the previous generation system include improved deflection systems, stage metrology, pattern data handling, and an address grid down to 10 nanometers. this system's specified performance enables it to produce reticles designed to support semiconductor fabrication utilizing 250 nanometer design rules, and beyond, with high accuracy and productivity.
Withthe ongoing shrinking of design rules, the complexity of photomasks does increase continuously. Features are getting smaller and denser, their characterization requires sophisticated procedures. Looking for the d...
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ISBN:
(纸本)0819431397
Withthe ongoing shrinking of design rules, the complexity of photomasks does increase continuously. Features are getting smaller and denser, their characterization requires sophisticated procedures. Looking for the deviation from their target value (CD-offtarget) and their linewidth variation (CD-uniformity) is not sufficient any more. In addition, measurements of corner rounding and line end shortening are necessary to define the pattern fidelity on the mask. Otherwise printing results will not be satisfying. Contacts and small features are suffering mainly from imaging inaccuracies. the size of the contacts as an example may come out too small on the photomask and therefore reduces the process window in lithography. In order to meet customer requirements for pattern fidelity, a measurement algorithm and a measurement procedure (e.g. implementing of test patterns on critical layers) needs to be introduced and specifications to be defined. In this paper different approaches are compared, allowing an automatic qualification of photomasks by optical light microscopy based on a MueTec CD-metrology system, the newly developed MueTec 2030UV, provided with a 365 nm light source (i-line). the i-line illumination allows to resolve features down to 0.2 mu m size with good repeatability.
Extreme ultraviolet lithography (EUVL) is one of the leading candidates for the next generation lithography, which will decrease critical feature size to below 100 nm within 5 years. mask fabrication is one of the key...
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Extreme ultraviolet lithography (EUVL) is one of the leading candidates for the next generation lithography, which will decrease critical feature size to below 100 nm within 5 years. mask fabrication is one of the key challenges in EUVL. the mask blank is a silicon wafer coated with 40 pairs of Mo and Si, designed to maximize reflectivity at 13.4 nm. the mask blank is coated with an absorbing film that is patterned withthe desired integrated circuit features using conventional mask patterning lithography, followed by reactive ion etching. the technical approaches to fabricating EUVL mask blanks and patterning mask absorber features are presented.
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