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Invasive programming as a concept for HPC

Invasive programming as a concept for HPC

引用

10th iasted international conference on parallel and distributed computing and Networks, PDCN 2011

作者： Bader, Michael Bungartz, Hans-Joachim Gerndt, Michael Hollmann, Andreas Weidendorfer, Josef Institute for Parallel and Distributed Systems Universität Stuttgart Universitätsstr. 38 70569 Stuttgart Germany Institute for Informatics Technische Universität München Boltzmannstr. 3 85748 Garching Germany

ISBN: (纸本)9780889868649

this paper introduces invasive computing, a new paradigm for programming parallel architectures. the goals are to enable the development and execution of resource aware programs that can dynamically allocate and free new resources in phases with more parallelism. To allocate more resources, applications use the invade operation and to free them the retreat. the research is conducted within the framework of the Transregional Collaborative Research Centre 89 funded by the German Science Foundation.

关键词： parallel architectures

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Skandium: Multi-core Programming with Algorithmic Skeletons

Skandium: Multi-core Programming with Algorithmic Skeletons

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18th Euromicro international conference on parallel, distributed and Network-Based Processing (PDP)

作者： Leyton, Mario Piquer, Jose M. Univ Chile NIC Labs Miraflores 222Piso 14 Santiago 8320198 Chile Univ Chile DCC Santiago Chile

ISBN: (纸本)9780769539393

this paper argues that algorithmic skeletons are a suitable programming model for multi-core architectures. the high-level abstractions offered by algorithmic skeletons provide a simple way for non-parallel programmers to address parallel programming. Previous algorithmic skeleton frameworks and libraries have addressed distributed computing environments such as Clusters and Grids. this paper proposes a parallel skeleton library, Skandium;and concludes, after an experimental evaluation, that algorithmic skeletons are an effective methodology to program multi-core architectures.

关键词： parallel programming multi-core patterns algorithmic skeletons

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parallel detection of nondeterministic races with provable correctness and efficiency

Parallel detection of nondeterministic races with provable c...

引用

Proceedings of the 16th iasted international conference on parallel and distributed computing and systems

作者： Yuxiong, He Junqing, Wang Jing, Hsu Wen Singapore MIT Alliance Singapore MIT Alliance Nanyang Technological University

We present a novel dynamic on-the-fly race detection mechanism called parallel Nondeterminator to check for determinacy races during the parallel execution of a program with Spawn-Sync parallelism. the parallel Nondeterminator provides provable correctness and efficiency. Let D denote the maximum depth of the recursion in the parallel program. the worst case slowdown in execution incurred for each spawn operation is O(D), the overhead for each sync operation is O(1) and the time required to monitor any shared memory access is O(log D). Moreover, we have implemented the parallel Nondeterminator in Cilk, a parallel language developed at MIT. Both theoretical and experimental results give strong evidences for the efficiency of our algorithm.

关键词： parallel processing systems

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parallel Harmony Search Based distributed Energy Resource Optimization 18

Parallel Harmony Search Based Distributed Energy Resource Op...

引用

2015 18th international conference on Intelligent System Application to Power systems (ISAP)

作者： Ceylan, Oguzhan Liu, Guodong Tomsovic, Kevin Univ Tennessee Dept Elect Engn & Comp Sci Knoxville TN 37996 USA Oak Ridge Natl Lab Power & Energy Syst Grp Oak Ridge TN 37381 USA

ISBN: (纸本)9781509001910

this paper presents a harmony search based parallel optimization algorithm to minimize voltage deviations in three phase unbalanced electrical distribution systems and to maximize active power outputs of distributed energy resources (DR). the main contribution is to reduce the adverse impacts on voltage profile during a day as photovoltaics (PVs) output or electrical vehicles (EVs) charging changes throughout a day. the IEEE 123-bus distribution test system is modified by adding DRs and EVs under different load profiles. the simulation results show that by using parallel computing techniques, heuristic methods may be used as an alternative optimization tool in electrical power distribution systems operation.

关键词： Linear programming Optimization Power distribution Program processors Sociology Statistics Voltage control

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A Cache-Aware parallel Implementation of the Push-Relabel Network Flow Algorithm and Experimental Evaluation of the Gap Relabeling Heuristic 18

A Cache-Aware Parallel Implementation of the Push-Relabel Ne...

引用

18th international conference on parallel and distributed computing systems, PDCS 2005

作者： Bader, David A. Sachdeva, Vipin College of Computing Georgia Institute of Technology AtlantaGA30332 United States Electrical and Computer Engineering Department University of New Mexico AlbuquerqueNM87106 United States

ISBN: (纸本)9781604234565

the maximum flow problem is a combinatorial problem of significant importance in a wide variety of research and commercial applications. It has been extensively studied and implemented over the past 40 years. the push-relabel method has been shown to be superior to other methods, both in theoretical bounds and in experimental implementations. Our study discusses the implementation of the push-relabel network flow algorithm on present-day symmetric multiprocessors (SMP’s) with large shared memories. the maximum flow problem is an irregular graph problem and requires frequent fine-grained locking of edges and vertices. Over a decade ago, Anderson and Setubal implemented Goldberg’s push-relabel algorithm for shared memory parallel computers;however, modern systems differ significantly from those targeted by their implementation in that SMP’s today have deep memory hierarchies and different performance costs for synchronization and fine-grained locking. Besides our new cache-aware implementation of Goldberg’s parallel algorithm for modern shared-memory parallel computers, our main new contribution is the first parallel implementation and analysis of the gap relabeling heuristic that runs from 2.1 to 4.3 times faster for sparse graphs. © 2005 18th ISCA international conference on parallel and distributed computing systems 2005, PDCS 2005. All rights reserved.

关键词： Memory architecture

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Massively parallel reconfigurable system architecture. POPA

Massively parallel reconfigurable system architecture. POPA

引用

Proceedings of the 4th ISMM/iasted international conference on parallel and distributed computing and systems

作者： Jaong, C.-S. Choi, J.-J. Lee, J.-Y.

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Processor partitioning: An experimental performance analysis of parallel applications on SMP cluster systems

Processor partitioning: An experimental performance analysis...

引用

19th iasted international conference on parallel and distributed computing and systems

作者： Wu, Xingfu Taylor, Valerie Department of Computer Science Texas A and M University College Station TX 77843 United States

ISBN: (纸本)9780889867048

Currently, clusters of shared memory symmetric multiprocessors (SMPs) are one of the most common parallel computing systems, for which some existing environments have between 8 to 32 processors per node. Examples of such environments include some supercomputers: DataStar p655 (P655 and P655m) and P690 at the San Diego Supercomputing Center, and Seaborg and Bassi at the DOE National Energy Research Scientific computing Center. In this paper, we quantify the performance gap resulting from using different number of processors per node for application execution (for which we use the term processor partitioning), and conduct detailed performance experiments to identify the major application characteristics that affect processor partitioning. We use the STREAM memory benchmarks and Intel's MPI benchmarks to explore the performance impact of different application characteristics. the results are then utilized to explain the performance results of processor partitioning using three NAS parallel Application benchmarks. the experimental results indicate that processor partitioning can have a significant impact on performance of a parallel scientific application as determined by its communication and memory requirements.

关键词： Supercomputers

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parallel Processing of Massive EEG Data with MapReduce

Parallel Processing of Massive EEG Data with MapReduce

引用

IEEE 18th international conference on parallel and distributed systems (ICPADS)

作者： Wang, Lizhe Chen, Dan Ranjan, Rajiv Khan, Samee U. Kolodziej, Joanna Wang, Jun Chinese Acad Sci Ctr Earth Observat & Digital Earth Beijing 100864 Peoples R China China Univ Geosciences Sch Comp Beijing Peoples R China CSIRO ICT Ctr Informat Engn lab Marshfield 2122 WI USA N Dakota State Univ Dept Elect & Comp Engn Grand Forks ND 58201 USA Univ Technol Inst Comp Sci Krakow Poland Univ Cent Florida Dept Elect Engn & Comp Sci Orlando FL 32816 USA

ISBN: (纸本)9781467345651;9780769549033

Analysis of neural signals like electroencephalogram (EEG) is one of the key technologies in detecting and diagnosing various brain disorders. As neural signals are non-stationary and non-linear in nature, it is almost impossible to understand their true physical dynamics until the recent advent of the Ensemble Empirical Mode Decomposition (EEMD) algorithm. the neural signal processing with EEMD is highly compute-intensive due to the high complexity of the EEMD algorithm. It is also data-intensive because 1) EEG signals contain massive data sets 2) EEMD has to introduce a large number of trials in processing to ensure precision. the MapReduce programming mode is a promising parallel computing paradigm for data intensive computing. To increase the efficiency and performance of the neural signal analysis, this research develops parallel EEMD neural signal processing with MapReduce. In this paper, we implement the parallel EEMD with Hadoop in a modern cyberinfrastructure. Test results and performance evaluation show that parallel EEMD can significantly improve the performance of neural signal processing.

关键词： Data-intensive computing MapReduce parallel processing parallel PROCESSING (COMPUTERS) signal processing Electroencephalography Brain Diseases Key technology MAPPING(MAthEMATICAL) Signal analysis data parallel computing data flow computing

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Performance of portable shared memory based parallel string matching software

Performance of portable shared memory based parallel string ...

引用

Proceedings of the 16th iasted international conference on parallel and distributed computing and systems

作者： Park, Jin Hwan Department of Computer Science State Univ. of New York at New Paltz New Paltz NY 12561 United States

In this paper, efficient and portable shared memory based parallel computation models for the string matching problem are presented and analyzed for their performances. For exploiting the parallelism in the computation models, parallel broadcasting method that is a dataflow scheme is applied. thus the models are time and space efficient since they are based on the dataflow mechanism. Several computation models are designed and tested for checking the aspects that affect the parallel programming performance such as granularity, communication, and I/O. For the implementation, Java threads that is a built-in support for the portable parallel programming in the shared memory environment is used. Experimental results demonstrate that the computation models are practical, portable, and scalable parallel solutions to the problem, and the comparative testing reveals facts between the theory and the practice.

关键词： parallel processing systems

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A parallel voronoi diagram on hypercube computers

A parallel voronoi diagram on hypercube computers

引用

Proceedings of the 16th iasted international conference on parallel and distributed computing and systems

作者： Muhammad, Rashid Bin Department of Computer Science Kent State University United States

the Voronoi diagram of a set of n sites on the plane has application in many diverse areas such as Geographical Information systems (GIS), Visualization, Robotics, Computer Graphics and Computer Aided Design (CAD). Unfortunately, its construction is very costly for large input sizes, and fast parallel algorithms for the problem are desired. there are no known parallel algorithms for the problem that are optimal with respect to the time-processor product. Best sequential algorithms work in O(n lg(n)) time. In this paper, an O(lg3n) time parallel algorithm for constructing the Voronoi Diagram of a set of n sites in the plane is presented on a hypercube with n processors. Our technique parallelizes the well-known seemingly inherent sequential technique of Shamos and Hoey, and makes use of a number of special properties of the dividing polygonal chain and the Batcher's bitonic sort.

关键词： parallel processing systems

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