the proceedings contain 98 papers. the topics discussed include: high-speed PCAP configuration scrubbing on Zynq-7000 all programmable SoCs;boosting convergence of timing closure using feature selection in a learning-...
ISBN:
(纸本)9782839918442
the proceedings contain 98 papers. the topics discussed include: high-speed PCAP configuration scrubbing on Zynq-7000 all programmable SoCs;boosting convergence of timing closure using feature selection in a learning-driven approach;liquid: fast placement prototyping through steepest gradient descent movement;TeSHoP : a temperature sensing based hotspot-driven placement technique for FPGAs;search-based synthesis of approximate circuits implemented into FPGAs;fast hierarchical NPN classification;and hardware acceleration of feature detection and description algorithms on low-power embedded platforms.
the proceedings contain 131 papers. the topics discussed include: customizable domain-specific computing;in search of agile hardware;the evolution of architecture exploration of programmable devices;MUCCRA-cube: a 3D ...
ISBN:
(纸本)9781424438921
the proceedings contain 131 papers. the topics discussed include: customizable domain-specific computing;in search of agile hardware;the evolution of architecture exploration of programmable devices;MUCCRA-cube: a 3D dynamically reconfigurable processor with inductive-coupling link;fast critical sections via thread scheduling for FPGA-based multithreaded processors;a biophysically accurate floating point somatic neuroprocessor;compiler assisted runtime task scheduling on a reconfigurable computer;generating high-performance custom floating-point pipelines;exploring reconfigurable architectures for explicit finite difference option pricing models;towards a viable out-of-order soft core: copy-free, checkpointed register renaming;a runtime relocation based workflow for self dynamic reconfigurable systems design;improving logic density through synthesis-inspired architecture;and replace: an incremental placement algorithm for field-programmable gate arrays.
the proceedings contain 86 papers. the topics discussed include: a SAT-based timing driven place and route flow for critical soft ip;lightweight secure processor prototype on FPGA;an application-specific field-program...
ISBN:
(纸本)9781538685174
the proceedings contain 86 papers. the topics discussed include: a SAT-based timing driven place and route flow for critical soft ip;lightweight secure processor prototype on FPGA;an application-specific field-programmable tree ensemble architecture;facilitating easier access to FPGAs in the heterogeneous cloud ecosystems;a demo of FPGA aggressive voltage downscaling: power and reliability tradeoffs;digital pre-distortion implemented using FPGA;accelerated wire-speed packet capture at 200 Gbps;and vicilogic2.0 online learning and prototyping using pYNQ.
the proceedings contain 7 papers. the topics discussed include: accelerating human activity recognition systems on FPGAs through a DSL approach;accelerating design convergence of automata processing designs with a til...
ISBN:
(纸本)9783800750467
the proceedings contain 7 papers. the topics discussed include: accelerating human activity recognition systems on FPGAs through a DSL approach;accelerating design convergence of automata processing designs with a tiled hierarchy;impact of off-chip memories on HLS-generated circuits;libGalapagos: a software environment for prototyping and creating heterogeneous FPGA and CPU applications;run-time performance monitoring of heterogeneous Hw/Sw platforms using PAPI;ZUCL 2.0: virtualized memory and communication for ZYNQ UltraScale+ FPGAs;and OpenCL design flows for Intel and Xilinx FPGAs: using common design patterns and dealing with vendor-specific differences.
the proceedings contain 9 papers. the topics discussed include: using Linux FIFOs to allow flexible hardware/software communications on reconfigurable systems-on-chip;improved parallelization of legacy embedded softwa...
ISBN:
(纸本)9783800747238
the proceedings contain 9 papers. the topics discussed include: using Linux FIFOs to allow flexible hardware/software communications on reconfigurable systems-on-chip;improved parallelization of legacy embedded software on soft-core MPSoCs through automatic loop transformations;exact mapping of rewritten linear functions to configurable logic;ZUCL: a ZYNQ UltraScale+ framework for OpenCL HLS applications;unfolding and folding: a new approach for code restructuring targeting HLS for FPGAs;HatScheT: a contribution to agile HLS;LeFlow: enabling flexible fpga high-level synthesis of tensorflow deep neural networks;a case study in using OpenCL on FPGAs: creating an open-source accelerator of the AutoDock molecular docking software;and a journey into DSL design using generative programming: FPGA mapping of image border handling through refinement.
the proceedings contain 64 papers. the topics discussed include: a deep-learning framework for predicting congestion during FPGA placement;lightweight side-channel protection using dynamic clock randomization;executin...
ISBN:
(纸本)9781728199023
the proceedings contain 64 papers. the topics discussed include: a deep-learning framework for predicting congestion during FPGA placement;lightweight side-channel protection using dynamic clock randomization;executing ARMv8 loop traces on reconfigurable accelerator via binary translation framework;precise pointer analysis in high-level synthesis;LFTSM: lightweight and fully testable SEU mitigation system for Xilinx processor-based SoCs;a high throughput MobileNetV2 FPGA implementation based on a flexible architecture for depthwise separable convolution;hardware acceleration of Monte-Carlo sampling for energy efficient robust robot manipulation;and automated design of FPGAs facilitated by cycle-free routing.
the proceedings contain 71 papers. the topic discussed include: reducing dynamic power in streaming CNN hardware accelerators by exploiting computational redundancies;Limago: an FPGA-based open-source 100 GbE TCP/IP s...
ISBN:
(纸本)9781728148847
the proceedings contain 71 papers. the topic discussed include: reducing dynamic power in streaming CNN hardware accelerators by exploiting computational redundancies;Limago: an FPGA-based open-source 100 GbE TCP/IP stack;a high-performance CNN processor based on FPGA for MobileNets;measuring long wire leakage with ring oscillators in cloud FPGAs;real-time multi-pedestrian detection in surveillance camera using FPGA;pyramid: machine learning framework to estimate the optimal timing and resource usage of a high-level synthesis design;timing-aware routing in the RapidWright framework;and beyond the limits: SHA-3 in just 49 slices.
the proceedings contain 10 papers. the topics discussed include: a case for better integration of host and target compilation when using OpenCL for FPGAs;PCIeHLS: an OpenCL HLS framework;SOCAO: source-to-source OpenCL...
ISBN:
(纸本)9783800744435
the proceedings contain 10 papers. the topics discussed include: a case for better integration of host and target compilation when using OpenCL for FPGAs;PCIeHLS: an OpenCL HLS framework;SOCAO: source-to-source OpenCL compiler for Intel-Altera FPGAs;a highly efficient and comprehensive image processing library for C++-based high-level synthesis;accelerating Linux bash commands on FPGAs using partial reconfiguration;acceleration of solving quadratic assignment problems on programmable SoC using High level synthesis;spatial memory trace prediction;on the HLS design of bit-level operations and custom data types;and using GCC analysis techniques to enable parallel memory accesses in HLS.
the proceedings contain 45 papers. the topics discussed include: CFEACT: a CGRA-based framework enabling agile CNN and transformer accelerator design;FlexWalker: an efficient multi-objective design space exploration f...
ISBN:
(纸本)9798331530075
the proceedings contain 45 papers. the topics discussed include: CFEACT: a CGRA-based framework enabling agile CNN and transformer accelerator design;FlexWalker: an efficient multi-objective design space exploration framework for HLS design;fast switching activity estimation for HLS-produced dataflow circuits;KIT: kernel isotropic transformation of bilateral filters for image denoising on FPGA;LORA: a latency-oriented recurrent architecture for GPT model on multi-FPGA platform with communication optimization;StencilStream: a SYCL-based stencil simulation framework targeting FPGAs;SoGraph: a state-aware architecture for out-of-memory graph processing on HBM-equipped FPGAs;and a high-performance routing engine for large-scale FPGAs.
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